1022410 – 0001 Rev. 2
UMOD hardware theory of operation 3–17
The FIR/NCO and A/D converter both use the same clock so that
sampling of the signal and processing by the FIR/NCO and
demodulator ASICs are synchronous. The clock signal into the
demodulator ASIC is provided by the FIR/NCO as a byproduct of
the sample rate decimation process.
Signal demodulation is performed by the UDMOD ASIC (see
figure 3-9). The signal is processed by many sidechains which
perform the functions of:
•
Carrier recovery phase error detection
•
Bit timing recovery (BTR)
•
Receive power detection and AGC control
•
Acquisition sweep control
•
E
s
/N
o
determination
UDMOD ASIC
AGC TO RX IF
STAGE
CRL OUTPUT TO
RX FIR/NCO ASIC
I
Q
BTR
BTR
I, Q, R DATA
AND
SOFT DECISION
HARD/
SOFT
DECISION
AGC
AGC TO RX IF
STAGE
CONTROL
PROCESSOR
E /N
b
o
ESTIMATOR
CRL PHASE
DETECTOR
ACQUISITION
SWEEP
CRL OUTPUT TO
RX FIR/NCO ASIC
FROM RX
FIR/NCO ASIC
UDMOD ASIC
Figure 3-9
Demodulator circuit block diagram
CRL loop filtering is performed in the receive FIR/NCO ASIC.
AGC filtering takes place in a digital filter in the UDMOD ASIC.
Demodulator
