
1022410 – 0001 Rev. 2
3–18 UMOD hardware theory of operation
The output of the demodulator is I and Q demodulated data at the
transmitted symbol rate, each quantized to one sign bit and two
magnitude bits. Soft-decision mapping is configurable for BPSK
and QPSK operation.
The channel decoding section of the UMOD motherboard is
responsible for formatting the data after it has been demodulated.
The decoding circuitry (see figure 3-10) performs the functions
specified in IESS-308 (IDR) and IESS-309 (IBS) that relate to
forward error correction and descrambling.
Figure 3-10
Channel decoding circuit block diagram
I
INPUT
FIFO
Q
R
TQM
RD-EN
PHASE
ROTATOR
ROTATE
BIT
ALIGN
MUX
ALIGN
TES
DE-
SHUFFLER
DE-
PUNCTURE
RE-SYNC
VIT
DEC
SEQUENTIAL
DECODER
SELECT
DATA
SERIALIZER
DIFF
DEC
BPSK
DIFF
DEC
OH
CHANNEL
EXTRACTOR
R.S.
DEC
V.35
DES
RX DATA
OH
The channel coding circuit performs the following functions:
•
Descrambling data for energy dispersion purposes
•
Differential decoding for resolution of phase ambiguity in
the demodulator during initial acquisition and following
cycle slips
•
[Detecting the Overhead Channel Frame Marker and
extracting the data packet]
•
Converting FEC Rate 1/2 to Rate 3/4 or Rate 7/8
(Puncturing)
•
Viterbi Decoding
Text inside of brackets—[ ]—denotes features currently under development.
Channel decoding