HP ESG-D Series, User Manual

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7-13
Operation
Frame/Pattern Triggering (Option 1EH)
Triggering a Continuous Pattern
To trigger a continuous pattern, the trigger must be sampled low on a data clock
rising edge and then be sampled high on the next, or some later, clock rising edge.
(The same as for a single pattern.) The pattern runs while the trigger input remains
high. When the trigger makes a high to low transition, the pattern stops and is
reset to the first bit.
If there is no input to the PATTERN TRIG IN connector, it is internally pulled to a
high state. A continuous pattern is output once the pattern repeat is set to
continuous. The pattern will not start or run if the trigger is held low at the
PATTERN TRIG IN connector. The signal generator does not have the capability
to over-ride a low user input and force the pattern to run.
In the continuous pattern mode, while waiting for the trigger to be sampled high,
the I and Q outputs will continue to clock and send phase transitions controlled by
the first symbol data and the symbol sync state in the pattern.
Frame versus Pattern Length
The pattern generation of the PN9 sequences in the signal generator is
RAM-based. As a result, framed patterns of PN9 data consist of multiple (511)
frames. A pattern is reset to the beginning at each trigger. Therefore, if the pattern
trigger occurs at the frame rate, and a multiple frame pattern is selected, only the
first frame of that pattern will be transmitted.
If a pattern is to be a single frame in length, the data in the frame must be a
four-bit pattern.
Pattern Trig In
Data Clock
Data
Pattern
No
Pattern
Transmission
Transmission
Transmission
No
Transmission