HP 16555A, Service Manual

Page: 10 / 141

Specifications
The specifications are the performance standards against which the product is tested.
Minimum State Clock Pulse Width
1
3.5 ns
Threshold Accuracy
±
(100 mV + 3% of threshold setting)
Clock Scheme:
Single Clock, Single Edge:
Setup/Hold Time:
1
0.0/3.5 ns through 3.5/0.0 ns,
adjustable in 500-ps increments
Maximum State Speed 110 MHz
2
Minimum Master-to-Master Clock Time
1
9.09 ns
2
Single Clock, Multiple Edges:
Setup/Hold Time:
1
0.0/4.0 ns through 4.0/0.0 ns,
adjustable in 500-ps increments
Maximum State Speed 100 MHz
Minimum Master-to-Master Clock Time
1
10.0 ns
Multiple Clocks, Multiple Edges:
Setup/Hold Time:
1
0.0/4.5 ns through 4.5/0.0 ns,
adjustable in 500-ps increments
Maximum State Speed 100 MHz
Minimum Master-to-Master Clock Time
1
10.0 ns
1
Specified for an input signal VH =
−
0.9 V, VL =
−
1.7 V, and threshold =
−
1.3 V.
2
An HP 16555A in an HP 16500B mainframe using operating system v2.xx has maximum state speed of 100 MHz and minimum
Master-to-Master Clock Time of 10.0 ns for single-clock, single-edge clocking. 110-MHz single-clock state acquisition mode is
available with HP 16500B mainframe operating system v3.00 or higher or HP 16500C mainframe operating system v1.00 or higher
(refer to "Operating System"). The maximum state acquisition speed is 100 MHz for all other clocking modes.
General Information
Specifications
1–3