3
Using the Delay mode of the pulse generator channel 1, position the pulses
according to the setup/hold combination selected, +0.0 ps or -100 ps.
a
On the Oscilloscope, select [Define meas] Define
∆
Time - Stop edge: rising.
b
In the oscilloscope timebase menu, select Position. Using the oscilloscope knob,
position the rising edge of the clock waveform so that it is centered on the display.
c
On the oscilloscope, select [Shift]
∆
Time, then select [Enter] to display the setup time
(
∆
Time(1)-(2)).
d
Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
4
Select the clock to be tested.
a
In the Master Clock menu, touch the clock field to be tested and then select the clock
edge as indicated in the table. The first time through this test, select the first clock
and edge.
Clocks
J
↑
K
↑
L
↑
M
↑
b
Touch Done to exit the Master Clock menu.
Note: The Master Clock menu shown is for an HP 16555A 1M Sample analyzer running in 110-MHz mode. If HP 16555A operating
system version v2.xx is being used, the Master Clock menu will look similar to that shown on page 3-38.
Testing Performance
To test the single-clock, single-edge, state acquisition
3–26
Summary of Contents for 16555A
Page 4: ...The HP 16555A D Logic Analyzer iii ...
Page 15: ...1 8 ...
Page 97: ...3 70 ...
Page 98: ...4 Calibrating ...
Page 102: ...Troubleshooting Flowchart 1 Troubleshooting To use the flowcharts 5 3 ...
Page 103: ...Troubleshooting Flowchart 2 Troubleshooting To use the flowcharts 5 4 ...
Page 104: ...Troubleshooting Flowchart 3 Troubleshooting To use the flowcharts 5 5 ...
Page 105: ...Troubleshooting Flowchart 4 3 Troubleshooting To use the flowcharts 5 6 ...
Page 117: ...5 18 ...
Page 125: ...6 8 ...
Page 131: ...7 6 ...
Page 132: ...8 Block Level Theory 8 2 Self Tests Description 8 6 Theory of Operation ...