5
In the logic analyzer Format menu, touch Run. The display should show an
alternating pattern of AA and 55. If the "Search Failed" yellow bar message does not
appear, the test passes. Record the Pass or Fail results in the performance test
record.
6
Enable the pulse generator channel 2 COMP (LED on).
7
Using the Delay mode of the pulse generator channel 1, position the pulses
according to the setup/hold combination selected, +0.0 ps or -100 ps.
a
On the Oscilloscope, select [Define meas] Define
∆
Time - Stop edge: falling.
b
On the oscilloscope, select [Shift] - width: channel 2, then select [Enter] to verify the
clock signal pulse width (- width (2)). If the pulse width is outside the limits, adjust the
pulse generator channel 2 width until the clock pulse width is 3.480 ns, +20 ps or -80
ps.
c
On the oscilloscope, select [Shift]
∆
Time. Select Start src: channel 1, then select
[Enter] to display the setup time (
∆
Time(1)-(2)).
d
Adjust the pulse generator channel 1 Delay until the pulses are aligned according the
the setup time of the setup/hold combination selected, +0.0 ps or -100 ps.
Testing Performance
To test the multiple-clock, multiple-edge, state acquisition
3–39
Summary of Contents for 16555A
Page 4: ...The HP 16555A D Logic Analyzer iii ...
Page 15: ...1 8 ...
Page 97: ...3 70 ...
Page 98: ...4 Calibrating ...
Page 102: ...Troubleshooting Flowchart 1 Troubleshooting To use the flowcharts 5 3 ...
Page 103: ...Troubleshooting Flowchart 2 Troubleshooting To use the flowcharts 5 4 ...
Page 104: ...Troubleshooting Flowchart 3 Troubleshooting To use the flowcharts 5 5 ...
Page 105: ...Troubleshooting Flowchart 4 3 Troubleshooting To use the flowcharts 5 6 ...
Page 117: ...5 18 ...
Page 125: ...6 8 ...
Page 131: ...7 6 ...
Page 132: ...8 Block Level Theory 8 2 Self Tests Description 8 6 Theory of Operation ...