Acquisition
The four clocks sent to the master card are also sent to the acquisition ICs
on the expander card. The acquisition ICs on the expander card individually generate
their own sample clock for the state acquisition mode. For timing acquisition mode, the
master card also passes the synchronization signal to the expander card.
The four clock/data lines on the expander card pods are not available for either state mode
clocking or state clock qualification. However, the four clock/data lines are still available as
data channels.
Test and Clock Synchronization Circuit
The signals generated by the Test and Clock
Synchronization Circuit of the master card are sent to the expander card. Consequently,
the Test and Clock Synchronization Circuit on the expander card is disabled to allow the
master configured card to drive the expander configured card. The functionality of the
Test and Clock Synchronization Circuit remains the same, but the circuit drives up to four
more Acquisition IC and up to eight more comparator test inputs.
Threshold
The thresholds of each of the expander card pods are individually
programmable, as with the master card pods. The threshold of the data and clock/data
channels of each pod is set to the same threshold voltage. The clock/data channel on each
pod of the expander card is available only as a data channel.
Self-Tests Description
The self-tests for the logic analyzer identify the correct operation of major functional areas in
the module. There are two sets of self-tests: the Board Verification Tests and the Acquisition
IC Verification Tests. The self-tests are not intended for component-level diagnostics.
Board Verification Tests
The Board Verification Tests functionally verify the main subsystems of the module other than
the acquisition ICs. Five tests are performed on the module subsystems. The tests are the
PLD, Oscillator, Data Memory, Alignment, and Comparators Tests.
PLD Test
Programmable Logic Devices (PLD) are utilized as an interface between the
HP 16500B/C Logic Analysis System backplane and the logic analyzer module. The PLD
Test verifies the operation of the data bus through the PLD. Test patterns are sent to the
module and are written to a block of module memory. The patterns are then read and
compared with known values. Also, a HW acceleration test verifies the PLD’s high-speed
pattern search operation.
Passing the PLD Test implies that the PLD is not corrupted and that data can be passed
between the logic analyzer module and the backplane of the 16500B/C mainframe.
Oscillator Test
The Oscillator Test functionally verifies the two oscillators and the
oscillator internal pathways on the logic analyzer module. The oscillators are checked
using the event counter on one of the acquisition ICs. The event counter will count the
number of oscillator periods within a pre-determined time window. The count of
oscillator periods is then compared with a known value.
Passing the Oscillator Test implies that both oscillators on the logic analyzer module are
operating properly.
Theory of Operation
Self-Tests Description
8–6
Summary of Contents for 16555A
Page 4: ...The HP 16555A D Logic Analyzer iii ...
Page 15: ...1 8 ...
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Page 98: ...4 Calibrating ...
Page 102: ...Troubleshooting Flowchart 1 Troubleshooting To use the flowcharts 5 3 ...
Page 103: ...Troubleshooting Flowchart 2 Troubleshooting To use the flowcharts 5 4 ...
Page 104: ...Troubleshooting Flowchart 3 Troubleshooting To use the flowcharts 5 5 ...
Page 105: ...Troubleshooting Flowchart 4 3 Troubleshooting To use the flowcharts 5 6 ...
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Page 132: ...8 Block Level Theory 8 2 Self Tests Description 8 6 Theory of Operation ...