GV GVA-AD6645 User Manual Download

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GV-395 Virtex-II DSP Hardware Accelerator Manual

GV & Associates, Inc.

07/10/04

D/A .........................................................................................................39

13.4.1

Single-Ended Output Path ...................................................................................................................39

13.4.2

Differential Coupled Analog Output Path ...........................................................................................39

13.4.3

GVA-DA9762 Analog Output Configuration.......................................................................................39

13.4.3.1

GVA-DA9762 Analog Output Jumper Configuration Table ....................................................................... 39

13.4.3.2

GVA-DA9762 to GVA-395 Interface Table................................................................................................ 40

13.4.3.3

GVA-DA9762 to GVA-395 AC FPGA PC No. 2-5 Connection Table ....................................................... 40

13.4.3.4

GVA-DA9762 to GVA-395 AC FPGA PC No. 6-9 Connection Table ....................................................... 41

D/A .........................................................................................................42

13.5.1

Single-Ended Output Path ...................................................................................................................42

13.5.2

Differential Coupled Analog Output Path ...........................................................................................42

13.5.3

GVA-DA9772 Analog Output Configuration.......................................................................................42

13.5.3.1

GVA-DA9772 Analog Output Jumper Configuration Table ....................................................................... 42

13.5.4

GVA-DA9772 PLL Configuration.......................................................................................................42

13.5.4.1

GVA-DA9772 to GVA-395 Interface Table................................................................................................ 43

13.5.4.2

GVA-DA9772 to GVA-395 AC FPGA PC No. 2-5 Connection Table ....................................................... 44

13.5.4.3

GVA-DA9772 to GVA-395 AC FPGA PC No. 6-9 Connection Table ....................................................... 45

14.0

GVA-395 CONFIGURATION JUMPER SETTINGS ...............................................................................46

14.1.1

GVA-395 Jumper Configuration Table................................................................................................46

15.0

GVA-395 TEST POINT DESCRIPTION....................................................................................................47

16.0

APPENDIX A: GVA-395 HARDWARE ACCELERATOR SCHEMATIC............................................48

17.0

APPENDIX B: GVA-395 SELF TEST FGPA SCHEMATIC ..................................................................49

18.0

APPENDIX C: GVA-395 FLASH EEPROM DOWNLOAD AND SYSTEM CLOCK

CONFIGURATION SPARTAN-II SCHEMATIC.................................................................................................50

Summary of Contents for GVA-AD6645

Page 1: ...GVA 395 Virtex II Hardware Accelerator User s Manual GV Associates Inc 23540 Oriente Way Ramona CA 92065 760 789 7015 www gvassociates com ...

Page 2: ... PC2 Interconnection Table 9 8 1 1 2 ACX FPGA U10 to PC3 and PC4 Interconnection Table 10 8 1 1 3 ACX FPGA U10 to PC6 and PC7 Interconnection Table 11 8 1 1 4 ACX FPGA U10 to PC8 and PC9 Interconnection Table 12 8 2 ACX FPGA HP LOGIC ANALYZER MICTOR CONNECTOR 13 8 2 1 1 ACX FPGA U10 to HC1 Interconnection Table 13 8 3 ACX FPGA 256K X 16 ZBT RAM 14 8 3 1 ACX FPGA U10 ZBT RAM Pin Configuration Table...

Page 3: ...ternal Interface FPGA Bus Interconnection Table for J1 29 12 2 2 External Interface FPGA Bus Interconnection Table for J2 29 12 3 EI FPGA LED 29 13 0 OPTIONAL DAUGHTER I O PCBS FOR ANALOG CONTROL FPGA U14 DESCRIPTIONS 30 13 1 GVA AD9430 170 MSPS 12 BIT A D 30 13 1 1 AC Coupled Analog Input Path 30 13 1 2 GVA AD9430 Output Configuration 30 13 1 2 1 GVA AD9430 to GVA 395 PC Connection Interface Tabl...

Page 4: ...le Ended Output Path 42 13 5 2 Differential Coupled Analog Output Path 42 13 5 3 GVA DA9772 Analog Output Configuration 42 13 5 3 1 GVA DA9772 Analog Output Jumper Configuration Table 42 13 5 4 GVA DA9772 PLL Configuration 42 13 5 4 1 GVA DA9772 to GVA 395 Interface Table 43 13 5 4 2 GVA DA9772 to GVA 395 AC FPGA PC No 2 5 Connection Table 44 13 5 4 3 GVA DA9772 to GVA 395 AC FPGA PC No 6 9 Connec...

Page 5: ...ocal buses connecting the ACX AC DP and the DPX FPGAs Additionally there is a shared 43 bit local buses between the ACX AC DP DPX and the EI FPGAs The external interface Spartan II FPGA EI is used to provide a 5V CMOS tolerant interface between the Virtex II FPGAs and other external devices However this FPGA could be used for additional processing as determined by the user Using the 48 bit externa...

Page 6: ...GV 395 Virtex II DSP Hardware Accelerator Manual GV Associates Inc 07 10 04 5 1 1 1 GVA 395 DSP Demonstration Platform Block Diagram ...

Page 7: ...routine 1 Insure that a jumper block is on the jumper block at JP5 and JP9 2 Connect the power cable to at least a 3 A 5V regulated power supply as describe in Section 2 0 3 Attach a 34 wire ribbon cable to J1 and J2 for the LVDS loop back test 4 Attach a 34 wire ribbon cable to J4 and J5 for the LVTTL loop back test 5 Apply power to the GVA 395 6 Verify that the proper voltages are present 5V TP8...

Page 8: ...the Slave Serial configuration mode This is further described in the section below The Virtex II FGPA at U10 will be configured first then the Virtex II FPGA at U12 then the Virtex II FPGA at U14 then the Virtex II FPGA at U16 and finally the Spartan II FPGA at U18 4 4 Slave Serial Programming of On Board EEPROM U2 1 Install the jumper blocks on JP1 JP2 and JP9 2 Remove the jumper blocks from JP3 ...

Page 9: ...e the on board system clock which has a SG 615 form factor such as those found in the Digi Key catalog The System clock is on pin AF18 for Virtex II FPGAs and on pin 15 of the Spartan II FPGAs To select the on board oscillator as the system clock connect a jumper block between pins1 and 2 of JP8 6 1 External Clock Configuration An exterior clock source P1 may be selected as the system clock by ins...

Page 10: ... 17 J1 AD1_DN8 17 N6 AD0_DP8 18 H2 AD1_DP8 18 P6 AD0_DN9 19 J3 AD1_DN9 19 T2 AD0_DP9 20 H3 AD1_DP9 20 R1 AD0_DN10 21 J4 AD1_DN10 21 T3 AD0_DP10 22 H4 AD1_DP10 22 R3 AD0_DN11 23 J5 AD1_DN11 23 R4 AD0_DP11 24 H5 AD1_DP11 24 P4 AD0_CLKN 25 U1 AD1_CLKN 25 U3 ADO_CLK 26 U2 AD1_CLK 26 V4 3 3V 27 No Connect 3 3V 27 No Connect 3 3V 28 No Connect 3 3V 28 No Connect 5V 29 No Connect 5V 29 No Connect 5V 30 N...

Page 11: ...19 AJ4 AD2_DP9 20 AE5 AD3_DP9 20 AK4 AD2_DN10 21 AE4 AD3_DN10 21 AF5 AD2_DP10 22 AF4 AD3_DP10 22 AG5 AD2_DN11 23 V5 AD3_DN11 23 AF6 AD2_DP11 24 W5 AD3_DP11 24 AG6 AD2_CLKN 25 V1 AD3_CLKN 25 W3 AD2_CLK 26 V2 AD3_CLK 26 Y3 3 3V 27 No Connect 3 3V 27 No Connect 3 3V 28 No Connect 3 3V 28 No Connect 5V 29 No Connect 5V 29 No Connect 5V 30 No Connect 5V 30 No Connect AD2_DN12 31 E17 GCLKP AD3_DN12 31 H...

Page 12: ...A1_DN9 19 P31 DA0_DP9 20 H31 DA1_DP9 20 N31 DA0_DN10 21 H29 DA1_DN10 21 P30 DA0_DP10 22 G29 DA1_DP10 22 N30 DA0_DN11 23 J29 DA1_DN11 23 N29 DA0_DP11 24 H28 DA1_DP11 24 P29 DA0_CLKN 25 V31 DA1_CLKN 25 U34 DA0_CLK 26 U31 DA1_CLK 26 U33 3 3V 27 No Connect 3 3V 27 No Connect 3 3V 28 No Connect 3 3V 28 No Connect 5V 29 No Connect 5V 29 No Connect 5V 30 No Connect 5V 30 No Connect DA0_DN12 31 K33 DA1_DN...

Page 13: ...A3_DN9 19 AG32 DA2_DP9 20 AB29 DA3_DP9 20 AF32 DA2_DN10 21 AB32 DA3_DN10 21 AG29 DA2_DP10 22 AC32 DA3_DP10 22 AH29 DA2_DN11 23 AD31 DA3_DN11 23 AH32 DA2_DP11 24 AC31 DA3_DP11 24 AJ32 DA2_CLKN 25 W32 DA3_CLKN 25 V30 DA2_CLK 26 V32 DA3_CLK 26 W30 3 3V 27 No Connect 3 3V 27 No Connect 3 3V 28 No Connect 3 3V 28 No Connect 5V 29 No Connect 5V 29 No Connect 5V 30 No Connect 5V 30 No Connect DA2_DN12 31...

Page 14: ...14 C12 HP0_SIG10 15 D12 HP0_SIG11 16 D13 HP0_SIG12 17 D10 HP0_SIG13 18 D11 HP0_SIG14 19 E8 HP0_SIG15 20 E9 HP0_SIG16 21 E13 HP0_SIG17 22 E14 HP0_SIG18 23 F14 HP0_SIG19 24 F13 HP0_SIG20 25 G12 HP0_SIG21 26 G13 HP0_SIG22 27 F15 HP0_SIG23 28 G15 HP0_SIG24 29 G16 HP0_SIG25 30 G17 HP0_SIG26 31 F16 HP0_SIG27 32 F17 HP0_SIG28 33 E11 HP0_SIG29 34 E10 HP0_SIG30 35 F10 HP0_SIG31 36 G9 HP0_SIG32 37 G10 HP0_S...

Page 15: ... B28 Data Bit 10 ZBT0_D10 B9 Address Bit 11 ZBT0_A11 B29 Data Bit 11 ZBT0_D11 B8 Address Bit 12 ZBT0_A12 B27 Data Bit 12 ZBT0_D12 B7 Address Bit 13 ZBT0_A13 B24 Data Bit 13 ZBT0_D13 B6 Address Bit 14 ZBT0_A14 B23 Data Bit 14 ZBT0_D14 B5 Address Bit 15 ZBT0_A15 B22 Data Bit 15 ZBT0_D15 B4 Address Bit 16 ZBT0_A16 B21 Data Bit 16 ZBT0_D16 B3 Address Bit 17 ZBT0_A17 C33 Data Bit 17 ZBT0_D17 C2 Address...

Page 16: ...J16 AJ16 XBUS21 AG11 AG11 XBUS71 AM15 AM15 XBUS22 AG12 AG12 XBUS72 AM14 AM14 XBUS23 AN7 AN7 XBUS73 AM16 AM16 XBUS24 AN6 AN6 XBUS74 AM17 AM17 XBUS25 AL10 AL10 XBUS75 AF17 AF17 XBUS26 AL9 AL9 XBUS76 AG17 AG17 XBUS27 AF12 AF12 XBUS77 AK16 AK16 XBUS28 AF13 AF13 XBUS78 AK17 AK17 XBUS29 AK10 AK10 XBUS79 AL30 AL30 XBUS30 AK11 AK11 XBUS80 AM31 AM31 XBUS31 AP7 AP7 XBUS81 AG24 AG24 XBUS32 AP6 AP6 XBUS82 AG2...

Page 17: ..._DN8 17 N6 DA4_DN8 17 P32 AD4_DP8 18 P6 DA4_DP8 18 N32 AD4_DN9 19 T2 DA4_DN9 19 P31 AD4_DP9 20 R1 DA4_DP9 20 N31 AD4_DN10 21 T3 DA4_DN10 21 P30 AD4_DP10 22 R3 DA4_DP10 22 N30 AD4_DN11 23 R4 DA4_DN11 23 N29 AD4_DP11 24 P4 DA4_DP11 24 P29 AD4_CLKN 25 U3 DA4_CLKN 25 U34 AD4_CLK 26 V4 DA4_CLK 26 U33 3 3V 27 No Connect 3 3V 27 No Connect 3 3V 28 No Connect 3 3V 28 No Connect 5V 29 No Connect 5V 29 No C...

Page 18: ...4 C12 HP1_SIG10 15 D12 HP1_SIG11 16 D13 HP1_SIG12 17 D10 HP1_SIG13 18 D11 HP1_SIG14 19 E8 HP1_SIG15 20 E9 HP1_SIG16 21 E13 HP1_SIG17 22 E14 HP1_SIG18 23 F14 HP1_SIG19 24 F13 HP1_SIG20 25 G12 HP1_SIG21 26 G13 HP1_SIG22 27 F15 HP1_SIG23 28 G15 HP1_SIG24 29 G16 HP1_SIG25 30 G17 HP1_SIG26 31 F16 HP1_SIG27 32 F17 HP1_SIG28 33 E11 HP1_SIG29 34 E10 HP1_SIG30 35 F10 HP1_SIG31 36 G9 HP1_SIG32 37 G10 HP1_SI...

Page 19: ...10 B28 Data Bit 10 ZBT1_D10 B9 Address Bit 11 ZBT1_A11 B29 Data Bit 11 ZBT1_D11 B8 Address Bit 12 ZBT1_A12 B27 Data Bit 12 ZBT1_D12 B7 Address Bit 13 ZBT1_A13 B24 Data Bit 13 ZBT1_D13 B6 Address Bit 14 ZBT1_A14 B23 Data Bit 14 ZBT1_D14 B5 Address Bit 15 ZBT1_A15 B22 Data Bit 15 ZBT1_D15 B4 Address Bit 16 ZBT1_A16 B21 Data Bit 16 ZBT1_D16 B3 Address Bit 17 ZBT1_A17 C33 Data Bit 17 ZBT1_D17 C2 Addre...

Page 20: ...AE29 G3 XBUS_A70 W27 M1 XBUS_A21 AF29 F3 XBUS_A71 Y27 L1 XBUS_A22 AE27 G2 XBUS_A72 AA29 P9 XBUS_A23 AF27 F2 XBUS_A73 AB29 R9 XBUS_A24 AK34 M10 XBUS_A74 AA31 P2 XBUS_A25 AL34 N10 XBUS_A75 AB31 N2 XBUS_A26 AD28 J6 XBUS_A76 Y29 R4 XBUS_A27 AE28 K6 XBUS_A77 Y28 P4 XBUS_A28 AD26 J5 XBUS_A78 AA33 R8 XBUS_A29 AE26 H5 XBUS_A79 AB33 T8 XBUS_A30 AG31 L7 XBUS_A80 AB30 T3 XBUS_A31 AF31 K7 XBUS_A81 AA30 R3 XBU...

Page 21: ...N32 AD5_DN8 17 G34 DA5_DN8 17 U30 AD5_DP8 18 F34 DA5_DP8 18 T30 AD5_DN9 19 J26 DA5_DN9 19 P31 AD5_DP9 20 K27 DA5_DP9 20 N31 AD5_DN10 21 E34 DA5_DN10 21 P30 AD5_DP10 22 D34 DA5_DP10 22 N30 AD5_DN11 23 G33 DA5_DN11 23 N27 AD5_DP11 24 F33 DA5_DP11 24 P27 AD5_CLKN 25 E33 DA5_CLKN 25 U28 AD5_CLK 26 D33 DA5_CLK 26 T28 3 3V 27 No Connect 3 3V 27 No Connect 3 3V 28 No Connect 3 3V 28 No Connect 5V 29 No C...

Page 22: ...4 C12 HP2_SIG10 15 D12 HP2_SIG11 16 D13 HP2_SIG12 17 D10 HP2_SIG13 18 D11 HP2_SIG14 19 E8 HP2_SIG15 20 E9 HP2_SIG16 21 E13 HP2_SIG17 22 E14 HP2_SIG18 23 F14 HP2_SIG19 24 F13 HP2_SIG20 25 G12 HP2_SIG21 26 G13 HP2_SIG22 27 F15 HP2_SIG23 28 G15 HP2_SIG24 29 G16 HP2_SIG25 30 G17 HP2_SIG26 31 F16 HP2_SIG27 32 F17 HP2_SIG28 33 E11 HP2_SIG29 34 E10 HP2_SIG30 35 F10 HP2_SIG31 36 G9 HP2_SIG32 37 G10 HP2_SI...

Page 23: ...B28 Data Bit 10 ZBT2_D10 B9 Address Bit 11 ZBT2_A11 B29 Data Bit 11 ZBT2_D11 B8 Address Bit 12 ZBT2_A12 B27 Data Bit 12 ZBT2_D12 B7 Address Bit 13 ZBT2_A13 B24 Data Bit 13 ZBT2_D13 B6 Address Bit 14 ZBT2_A14 B23 Data Bit 14 ZBT2_D14 B5 Address Bit 15 ZBT2_A15 B22 Data Bit 15 ZBT2_D15 B4 Address Bit 16 ZBT2_A16 B21 Data Bit 16 ZBT2_D16 B3 Address Bit 17 ZBT2_A17 C33 Data Bit 17 ZBT2_D17 C2 Address ...

Page 24: ...AE27 USB0_FD15 Bidirectional FIFO Command Data Bit 15 AG31 USB0_FD14 Bidirectional FIFO Command Data Bit 14 AF31 USB0_FD13 Bidirectional FIFO Command Data Bit 13 AG32 USB0_FD12 Bidirectional FIFO Command Data Bit 12 AF32 USB0_FD11 Bidirectional FIFO Command Data Bit 11 AB25 USB0_FD10 Bidirectional FIFO Command Data Bit 10 AC25 USB0_FD9 Bidirectional FIFO Command Data Bit 9 AH33 USB0_FD8 Bidirectio...

Page 25: ...1 AG11 AG11 XBUS_B71 AM15 AM15 XBUS_B22 AG12 AG12 XBUS_B72 AM14 AM14 XBUS_B23 AN7 AN7 XBUS_B73 AM16 AM16 XBUS_B24 AN6 AN6 XBUS_B74 AM17 AM17 XBUS_B25 AL10 AL10 XBUS_B75 AF17 AF17 XBUS_B26 AL9 AL9 XBUS_B76 AG17 AG17 XBUS_B27 AF12 AF12 XBUS_B77 AK16 AK16 XBUS_B28 AF13 AF13 XBUS_B78 AK17 AK17 XBUS_B29 AK10 AK10 XBUS_B79 AL30 AL30 XBUS_B30 AK11 AK11 XBUS_B80 AM31 AM31 XBUS_B31 AP7 AP7 XBUS_B81 AG24 AG...

Page 26: ...1 ZBTM_A11 B29 Data Bit 11 ZBTM_D11 B8 Address Bit 12 ZBTM_A12 B27 Data Bit 12 ZBTM_D12 B7 Address Bit 13 ZBTM_A13 B24 Data Bit 13 ZBTM_D13 B6 Address Bit 14 ZBTM_A14 B23 Data Bit 14 ZBTM_D14 B5 Address Bit 15 ZBTM_A15 B22 Data Bit 15 ZBTM_D15 B4 Address Bit 16 ZBTM_A16 B21 Data Bit 16 ZBTM_D16 B3 Address Bit 17 ZBTM_A17 C33 Data Bit 17 ZBTM_D17 C2 Address Bit 18 ZBTM_A18 C28 RAM ReDA Write ZBTM_R...

Page 27: ...AE27 USB1_FD15 Bidirectional FIFO Command Data Bit 15 AG31 USB1_FD14 Bidirectional FIFO Command Data Bit 14 AF31 USB1_FD13 Bidirectional FIFO Command Data Bit 13 AG32 USB1_FD12 Bidirectional FIFO Command Data Bit 12 AF32 USB1_FD11 Bidirectional FIFO Command Data Bit 11 AB25 USB1_FD10 Bidirectional FIFO Command Data Bit 10 AC25 USB1_FD9 Bidirectional FIFO Command Data Bit 9 AH33 USB1_FD8 Bidirectio...

Page 28: ...LVDS_RN11 AJ4 25 LVDS_RN4 AF5 9 LVDS_RP11 AK4 26 LVDS_RP4 AG5 10 LVDS_RN12 AK2 27 LVDS_RN5 AE8 11 LVDS_RP12 AL2 28 LVDS_RP5 AD8 12 LVDS_RN13 AH6 29 LVDS_RN6 AH1 13 LVDS_RP13 AJ5 30 LVDS_RP6 AJ1 14 LVDS_RN14 AE11 31 LVDS_RN7 AG4 15 LVDS_RP14 AF11 32 LVDS_RP7 AH5 16 LVDS_RN15 AF10 33 DGND 17 LVDS_RP15 AG9 34 11 4 1 DPX FPGA LVDS Bus Interconnection Table for J6 Signal DCX FPGA U16 Pin No J5 No Signa...

Page 29: ...J23 5 87 XE_BUS12 K23 K23 K23 K23 6 93 XE_BUS13 K22 K22 K22 K22 7 94 XE_BUS14 C26 C26 C26 C26 10 95 XE_BUS15 D27 D27 D27 D27 11 96 XE_BUS16 G24 G24 G24 G24 12 NC XE_BUS17 G25 G25 G25 G25 13 NC XE_BUS18 E25 E25 E25 E25 19 NC XE_BUS19 E24 E24 E24 E24 20 NC XE_BUS20 D25 D25 D25 D25 21 NC XE_BUS21 D26 D26 D26 D26 22 NC XE_BUS22 H23 H23 H23 H23 23 NC XE_BUS23 H22 H22 H22 H22 26 NC XE_BUS24 F23 F23 F23 ...

Page 30: ...14 EBUS22 103 31 EBUS10 84 15 EBUS23 112 32 EBUS11 85 16 DGND 33 DGND 17 DGND 34 12 2 1 External Interface FPGA Bus Interconnection Table for J1 Signal EI FPGA U14 Pin No J2 No Signal EI FPGA U20 Pin No J2 No DGND 1 DGND 18 DGND 2 EBUS36 129 19 EBUS24 113 3 EBUS37 130 20 EBUS25 114 4 DGND 21 EBUS26 115 5 DGND 22 EBUS27 116 6 EBUS38 131 23 EBUS28 117 7 EBUS39 132 24 EBUS29 118 8 EBUS40 133 25 EBUS3...

Page 31: ...GVA AD9430 Output Configuration Signal Name Signal Description PC Pin No Signal Name Signal Description PC Pin No D11 LVDS Output Data Bit 11 Complement 1 D1 LVDS Output Data Bit 1 22 D11 LVDS Output Data Bit 11 2 D0 LVDS Output Data Bit 0 Complement 23 D10 LVDS Output Data Bit 10 Complement 3 D0 LVDS Output Data Bit 0 24 D10 LVDS Output Data Bit 10 4 AD_CLK LVDS Input Clock Complement 25 D9 LVDS ...

Page 32: ...1 K4 AB5 AJ1 D7 9 G2 P2 AD1 AH2 D7 10 F2 N2 AC1 AJ2 D6 11 G3 N4 AC2 AH3 D6 12 F3 M4 AD2 AJ3 D5 13 F4 P3 AC3 AK2 D5 14 E4 N3 AD3 AL2 D4 15 F5 P5 AC4 AL1 D4 16 G5 N5 AD4 AK1 D3 17 J1 N6 AB6 AH6 D3 18 H2 P6 AC6 AJ5 D2 19 J3 T2 AD5 AJ4 D2 20 H3 R1 AE5 AK4 D1 21 J4 T3 AE4 AF5 D1 22 H4 R3 AF4 AG5 D0 23 J5 R4 V5 AF6 D0 24 H5 P4 W5 AG6 AD_CLK 25 U1 U3 V1 W3 AD_CLK 26 U2 U4 V2 Y3 DCO 31 E19 K18 E17 H17 DCO...

Page 33: ...F26 D6 12 F33 K29 Y27 AG26 D5 13 G32 L29 AB30 AF28 D5 14 F32 M29 AA30 AG28 D4 15 F30 P33 AA33 AF30 D4 16 G30 N33 AB33 AG30 D3 17 J34 P32 AA31 AG31 D3 18 H33 N32 AB31 AF31 D2 19 J31 P31 AA29 AG32 D2 20 H31 N31 AB29 AF32 D1 21 H29 P30 AB32 AG29 D1 22 G29 N30 AC32 AH29 D0 23 J29 N29 AD31 AH32 D0 24 H28 P29 AC31 AJ32 AD_CLK 25 V31 U34 W32 V30 AD_CLK 26 U31 U33 V32 W30 DCO 31 K33 R28 AC34 AK31 DCO 32 J...

Page 34: ... differential receiver MC10EL16 The output of this differential receiver drive the ENCODE and ENCODE inputs of the converter and provides the sub nanosecond rise times for optimum performance 13 2 1 AC Coupled Analog Input Path The analog input is AC coupled into two Mini Circuits T1 1 transformer which has a high pass corner at 50 KHz These transformers are used to generate a differential input t...

Page 35: ...C Data Bus 3 34 DGND Digital Ground 14 D_BUS4 Daughter PC Data Bus 4 35 AD0_D7 AD Output Bit 7 15 D_BUS5 Daughter PC Data Bus 5 36 DGND Digital Ground 16 D_BUS6 Daughter PC Data Bus 6 37 AD0_D8 AD Output Bit 8 17 D_BUS7 Daughter PC Data Bus 7 38 DGND Digital Ground 18 DGND Digital Ground 39 AD0_D9 AD Output Bit 9 19 DGND Digital Ground 40 DGND Digital Ground 20 DGND Digital Ground 41 AD0_D10 AD Ou...

Page 36: ...34 AD26 AD0_D1 3 E33 M34 V27 AD28 AD0_D2 5 E32 M33 V28 AE25 AD0_D3 7 F31 M32 W31 AE27 AD0_D4 9 G34 M31 Y29 AE29 AD0_D5 11 G33 L30 W27 AF26 AD0_D6 13 G32 L29 AB30 AF28 AD0_D7 15 F30 P33 AA33 AF30 AD0_D8 17 J34 P32 AA31 AG31 AD0_D9 19 J31 P31 AA29 AG32 AD0_D10 21 H29 P30 AB32 AG29 AD0_D11 23 J29 N29 AD31 AH32 AD0_CLK 25 V31 U34 W32 V30 13 2 3 4 GVA DA9432 to GVA 395 AC FPGA PC No 6 9 Connection Tabl...

Page 37: ... and ENCODE inputs of the converter and provides the sub nanosecond rise times for optimum performance 13 3 1 AC Coupled Analog Input Path The analog input is AC coupled into two Mini Circuits T1 1 transformer which has a high pass corner at 50 KHz These transformers are used to generate a differential input to the DA6645 To reduce the second harmonic distortion two T1 1T transformers are connecte...

Page 38: ... AD1 AD Output Bit 1 14 D_BUS4 DAughter PC DAta Bus 4 35 AD2 AD Output Bit 2 15 D_BUS5 DAughter PC DAta Bus 5 36 16 D_BUS6 DAughter PC DAta Bus 6 37 AD0 AD Output Bit 0 17 D_BUS7 DAughter PC DAta Bus 7 38 18 DGND Digital Ground 39 19 DGND Digital Ground 40 20 DGND Digital Ground 41 21 DGND Digital Ground 42 13 3 3 2 GVA DA6645 to GVA 395 Interface Table Signal Name PC Pin No AC FPGA PC 2 Pin No AC...

Page 39: ... 15 F30 P33 AA33 AF30 AD_D3 12 F33 K29 Y27 AG26 AD_D4 13 G32 L29 AB30 AF28 AD_D5 10 F34 L31 Y28 AF29 AD_D6 11 G33 L30 W27 AF26 AD_D7 8 E31 L32 Y31 AF27 AD_D8 9 G34 M31 Y29 AE29 AD_D9 6 D32 L33 W28 AF25 AD_D10 7 F31 M32 W31 AE27 AD_D11 4 D33 L34 V26 AE28 AD_D12 5 E32 M33 V28 AE25 AD_D13 2 D34 K30 V33 AE26 AD_OVR 1 E34 K31 V34 AD26 AD_DRY 3 E33 M34 V33 AE26 AD_CLK 25 V31 U34 W32 V30 13 3 3 4 GVA DA6...

Page 40: ...pproximately 0 V to 0 5 V for a doubly terminated 50 cable since the nominal full scale current 20 mA flows through the equivalent RLODA of 25 ohm In this case RLODA represents the equivalent loDA resistance seen by IOUTA or IOUTB The unused output IOUTA or IOUTB can be connected to ACOM directly or via a matching 25 ohm resistor 13 4 2 Differential Coupled Analog Output Path An RF transformer is ...

Page 41: ...a Bus 3 34 DGND Digital Ground 14 D_BUS4 Daughter PC Data Bus 4 35 DA0_D7 DA Output Bit 7 15 D_BUS5 Daughter PC Data Bus 5 36 DGND Digital Ground 16 D_BUS6 Daughter PC Data Bus 6 37 DA0_D8 DA Output Bit 8 17 D_BUS7 Daughter PC Data Bus 7 38 DGND Digital Ground 18 DGND Digital Ground 39 DA0_D9 DA Output Bit 9 19 DGND Digital Ground 40 DGND Digital Ground 20 DGND Digital Ground 41 DA0_D10 DA Output ...

Page 42: ...34 AD26 DA0_D1 3 E33 M34 V27 AD28 DA0_D2 5 E32 M33 V28 AE25 DA0_D3 7 F31 M32 W31 AE27 DA0_D4 9 G34 M31 Y29 AE29 DA0_D5 11 G33 L30 W27 AF26 DA0_D6 13 G32 L29 AB30 AF28 DA0_D7 15 F30 P33 AA33 AF30 DA0_D8 17 J34 P32 AA31 AG31 DA0_D9 19 J31 P31 AA29 AG32 DA0_D10 21 H29 P30 AB32 AG29 DA0_D11 23 J29 N29 AD31 AH32 DA0_CLK 25 V31 U34 W32 V30 13 4 3 4 GVA DA9762 to GVA 395 AC FPGA PC No 6 9 Connection Tabl...

Page 43: ...esents the equivalent loDA resistance seen by IOUTA or IOUTB The unused output IOUTA or IOUTB can be connected to ACOM directly or via a matching 25 ohm resistor 13 5 2 Differential Coupled Analog Output Path An RF transformer is be used to perform a differential to single ended signal conversion A differentially coupled transformer output provides the optimum distortion performance for output sig...

Page 44: ...DC Input 30 DA_D9 DA Output Bit 9 10 31 DA_D10 DA Output Bit 10 11 D_BUS1 Daughter PC Data Bus 1 32 DA_D11 DA Output Bit 11 12 D_BUS2 Daughter PC Data Bus 2 33 DA_D12 DA Output Bit 12 13 D_BUS3 Daughter PC Data Bus 3 34 DA_D13 DA Output Bit 13 14 D_BUS4 Daughter PC Data Bus 4 35 DIV1 Div Bit 1 15 D_BUS5 Daughter PC Data Bus 5 36 MOD1 zero stuffing option 16 D_BUS6 Daughter PC Data Bus 6 37 DIV0 Di...

Page 45: ..._D4 5 E3 M3 AA4 AF3 DA_D5 6 D3 L3 AB4 AG3 DA_D6 7 G1 L4 AA5 AH1 DA_D7 8 F1 K4 AB5 AJ1 DA_D8 9 G2 P2 AD1 AH2 DA_D9 10 F2 N2 AC1 AJ2 DA_D10 11 G3 N4 AC2 AH3 DA_D11 12 F3 M4 AD2 AJ3 DA_D12 13 F4 P3 AC3 AK2 DA_D13 14 E4 N3 AD3 AL2 DIV1 15 F5 P5 AC4 AL1 MOD1 16 G5 N5 AD4 AK1 DIV0 17 J1 N6 AB6 AH6 MOD0 18 H2 P6 AC6 AJ5 SLEEP 19 J3 T2 AD5 AJ4 PLLLOCK 20 H3 R1 AE5 AK4 RESET 21 J4 T3 AE4 AF5 DA_CLK 25 U1 U...

Page 46: ...D5 6 D32 L33 W28 AF25 DA_D6 7 F31 M32 W31 AE27 DA_D7 8 E31 L32 Y31 AF27 DA_D8 9 G34 M31 Y29 AE29 DA_D9 10 F34 L31 Y28 AF29 DA_D10 11 G33 L30 W27 AF26 DA_D11 12 F33 K29 Y27 AG26 DA_D12 13 G32 L29 AB30 AF28 DA_D13 14 F32 M29 AA30 AG28 DIV1 15 F30 P33 AA33 AF30 MOD1 16 G30 N33 AB33 AG30 DIV0 17 J34 P32 AA31 AG31 MOD0 18 H33 N32 AB31 AF31 SLEEP 19 J31 P31 AA29 AG32 PLLLOCK 20 H31 N31 AB29 AF32 RESET 2...

Page 47: ...iguration of the FPGAs via the JTAG Connector JP3 Installed Not Installed Not Installed Installed Enables the configuration of the FPGAs via the Slave Serial Connector JP7 Installed Not Installed Installed Not Installed Enables the configuration of the FPGAs via the on board FLASH EEPROM Installed Installed Not Installed Installed Enables the configuration of the FPGAs via the Slave Serial Connect...

Page 48: ... 4 Flash EEPROM Output Enable 5 Flash EEPROM Reset 6 Flash EEPROM Ready 7 Ground 8 VCC 9 3 3V 10 2 5V 11 1 5V 12 PT7711 Sync 13 PT7711 Standby 18 Additional Clock Output 19 System Clock 20 DPX ZBTM Chip Enable 0 21 DPX ZBTM Read Write 22 DPX ZBTM Output Enable 23 DPX ZBTM Clock 24 DPX ZBTM Chip Enable 1 28 DPX ZBTM Chip Enable 2 32 DPX ZBTM Chip Enable 3 38 AD0 Clock 96 VREF 97 VCCO ...

Page 49: ...GV 395 Virtex II DSP Hardware Accelerator Manual GV Associates Inc 07 10 04 48 16 0 Appendix A GVA 395 Hardware Accelerator Schematic ...

Page 50: ...GV 395 Virtex II DSP Hardware Accelerator Manual GV Associates Inc 07 10 04 49 17 0 Appendix B GVA 395 Self Test FGPA Schematic ...

Page 51: ...GV 395 Virtex II DSP Hardware Accelerator Manual GV Associates Inc 07 10 04 50 18 0 Appendix C GVA 395 Flash EEPROM Download and System Clock Configuration Spartan II Schematic ...

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