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General Standards Corporation

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MAN-PCIe-24DSI32

Summary of Contents for PCIe-24DSI32

Page 1: ...______________________________ General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com Rev 042514 PCIe 24DSI32 24 BIT 32 CHANNEL DELTA SIGMA 200 KSPS ANALOG...

Page 2: ...and Synchronization 2 4 2 4 1 Interboard Connections 2 4 2 4 2 Multiboard Synchronization 2 5 2 5 Maintenance 2 5 2 6 Reference Verification and Adjustment 2 5 2 6 1 Equipment Required 2 6 2 6 2 Adjus...

Page 3: ...6 2 2 Legacy Rate Generator 3 14 3 6 3 Direct External Clocking 3 14 3 6 4 Harmonically Locked Channels 3 15 3 6 5 Channel Synchronization 3 15 3 6 6 Multiboard Operation 3 15 3 6 6 1 External Sample...

Page 4: ...ata Registers 3 1 3 2 Board Control Register 3 2 3 3 1 Configuration Operations 3 3 3 4 Analog Input Function Selection 3 4 3 4 3 Analog Input Range Selection 3 4 3 5 2 Input Data Buffer Organization...

Page 5: ...ts consist of 3 3 VDC in accordance with the PCI specification and operation over the specified temperature range is achieved with minimal 200 LFPM air cooling Specific details pertaining to physical...

Page 6: ...ns and autocalibration Gain and offset trimming of the input channels is performed by applying correction values obtained during autocalibration PCI Conn I O Conn Analog Inputs 32 Diff Input Configura...

Page 7: ...et is located in the slot position remove the bracket Then remove the board from the shipping envelope and position the board with the panel bracket oriented toward the expansion panel opening Align t...

Page 8: ...INPUT RETURN 16 INPUT RETURN 17 INPUT CH 00 LO 17 INPUT CH 19 LO 18 INPUT CH 00 HI 18 INPUT CH 19 HI 19 INPUT CH 01 LO 19 INPUT CH 20 LO 20 INPUT CH 01 HI 20 INPUT CH 20 HI 21 INPUT CH 02 LO 21 INPUT...

Page 9: ...Inputs Differential operation is essential when the input source returns are at different potentials This operating mode also offers the highest rejection of the common mode noise that is characteris...

Page 10: ...n Analog input converters on multiple boards can be a Clocked from a single clock source Multiboard clocking and or b Synchronized to a common time reference Multiboard synchronization Clocking multip...

Page 11: ...nd also selects the channels on each board that will respond to the daisy chained clock Although only software designated channels respond to the daisy chained clock all channels on all target boards...

Page 12: ...r 5 1 2 digit 0 005 accuracy for DC voltage measurements at 10 Volts Hewlett Packard 34401A Host system with PCIe expansion slot Cable connector with test leads Not required if calibration test points...

Page 13: ...1 Connect the digital multimeter between the VTEST OUTPUT and VTEST RETURN pins in the system I O connector Refer to Table 2 2 2 for pin assignments 2 If power has been removed from the board apply po...

Page 14: ...00 R W Board Control BCR 0000 383Ch Board Control Register BCR 04 R W Nref PLL Control 0000 01F4h PLL reference oscillator control integer PLL configuration only 08 R W Nvco PLL Control Legacy Nrate...

Page 15: ...INTERRUPT A0 Interrupt event selection Default is zero D09 R W INTERRUPT A1 D10 R W INTERRUPT A2 D11 R W INTERRUPT REQUEST FLAG Set HIGH when the board requests an interrupt Clears the request when cl...

Page 16: ...PCIe interrupts disabled Attempts to access the local bus during configuration should be avoided until the PCIe interrupts are enabled and the initialization complete interrupt request is asserted 3...

Page 17: ...rify the accuracy of any or all input channels by replacing the system input connections with either a precision internal reference voltage VREF or a zero reference ZERO The VREF test produces a posit...

Page 18: ...cs Analog input samples accumulate in the analog input data FIFO data buffer which has a capacity of 256K 262 144 data values Data accumulates in the buffer until extracted by the PCI bus from a singl...

Page 19: ...e 5V range Negative Full Scale is the negative equivalent of positive full scale Full scale Range FSR is the total input voltage range For 16 Bit data one LSB equals the full scale range divided by 65...

Page 20: ...UT control bit is active in the BCR When this bit is set HIGH the threshold flag is routed to the AUX LVDS OUT output in the system I O connector 3 5 3 2 Buffer Clearing and Disabling Asserting the CL...

Page 21: ...ed either from an adjustable internal rate generator or from a single external hardware clock as shown in Figure 3 6 1 1 Input channels are arranged into four groups Table 3 6 1 1 three of which can b...

Page 22: ...Z Nvco Nref PLL Oscillator Mode Decode Rate Divisor Ndiv ADC Sample Clock Ch 00 31 Rate Gen Out Chan 00 Clock Initiator Local ADC Sync Ext Sync Output Target Initiator Internal Clocking Rate Assign 0...

Page 23: ...t Codes ASSIGNMENT CODE GROUP 0 ASSIGNMENT GROUPS 1 3 ASSIGNMENT 0 Internal Rate Generator Unused 1 Reserved Unused 2 Reserved Unused 3 Reserved Unused 4 External Sample Clock as rate generator input...

Page 24: ...a stable reference frequency Older Legacy versions of this product implement a rate generator that could be adjusted with 0 2 percent resolution The higher resolution PLL configuration however provide...

Page 25: ...ect the lowest possible values for Nvco and Nref Because specific applications might require custom values for Fref an approximate measurement of the installed PLL reference oscillator frequency is av...

Page 26: ...me factors and simplify the fraction by canceling all factors that are duplicated in the numerator and denominator 3 Select a value for DIVISOR that adjusts the value of the fraction to between 0 61 a...

Page 27: ...starts by selecting a maximum value for DIVISOR from Ndiv in Equation 3 1 and then selects successively smaller values of Ndiv until valid values for both Ndiv and Nrate produce a value for Fsamp tha...

Page 28: ...ion of the synchronization sequence is indicated by the CHANNELS READY flag in the BCR undergoing a Low to High transition Paragraph 3 4 4 The CHANNELS READY transition can be selected as a condition...

Page 29: ...rnal clock NOTE The INITIATOR control bit controls only the sources of the external clock and sync output signals and has no other effect Multiple boards can all be configured as initiators and operat...

Page 30: ...rs the AUTOCAL PASS status flag in the BCR will be LOW when the autocal sequence is completed A HIGH state for AUTOCAL PASS indicates that autocalibration was successful To ensure full conformance to...

Page 31: ...1 Interrupt Event Selection INTERRUPT A 2 0 INTERRUPT EVENT CONDITION 0 Initialization completed Default state 1 Autocal completed 2 Channels Ready 3 Data Buffer threshold flag LOW to HIGH transition...

Page 32: ...08h A8h D7 0 DMA Command Status Command and Status Register 01h 03h See Text Determined by specific transfer requirements 3 9 2 Demand Mode Demand mode transfers are controlled in a manner similar to...

Page 33: ...Note References to channel synchronization in this manual pertain to the situation in which the sampling of all input channels occurs simultaneously Scan synchronization refers to the synchronization...

Page 34: ...chronized mode and the sample clock settings for Group 1 through Group 3 are ignored Disabled groups remain disabled Use the following sequence to scan synchronize multiple boards Paragraph 3 6 3 Sync...

Page 35: ...e allows a burst to be initiated externally through the AUX I O pins in the system I O connector regardless of the selected rate assignment Paragraph 3 6 1 2 This feature is available with firmware re...

Page 36: ...hange Transitioning into or out of a selftest mode or out of autocalibration A system or local reset Power application The settling time required to reestablish specified performance depends upon the...

Page 37: ...PCIe 24DSI32 _____________________________________________________________________________ General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com 3 24...

Page 38: ...s including autocalibration PCI Conn I O Conn Analog Inputs 32 Diff Input Configuration Switches PCI Interface Adapter Voltage Reference V Test Out Sample Rate Generator s Local Controller Input Data...

Page 39: ...l controller then attaches a 5 bit channel tag to the data word applies offset and gain correction factors and finally transfers the corrected data to the input data buffer Antialias filtering is prov...

Page 40: ...Boards that receive and retransmit the external clock are clock targets Multiple targets can be controlled from a single initiator 4 5 Power Control Regulated supply voltages of 5 Volts 6 Volts and 1...

Page 41: ...________________________________________________________________________ General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com A 1 APPENDIX A LOCAL REGIST...

Page 42: ...01F4h PLL vco control integer Nrate for the legacy rate generator 0C R W Rate Assignments 0000 0000h ADC Clock source Group disables 10 R W Rate Divisor 0000 0005h Sample rate divisor 14 RO Reserved...

Page 43: ...sts an interrupt Clears the request when cleared LOW by the bus D12 RO AUTOCAL PASS Set HIGH at reset or autocal initialization Cleared LOW if autocalibration terminates unsuccessfully D13 RO CHANNELS...

Page 44: ...3 4 Analog Input Function Selection AIM 0 FUNCTION OR MODE 0 Differential analog input mode 1 Reserved 2 ZERO test Internal ground reference is connected to all analog input channels 3 VREF test Inter...

Page 45: ...T FIELD MODE DESIGNATION FUNCTION D 17 00 R W BUFFER THRESHOLD Buffer Flag Threshold duplicated in the BCR D 18 R W DISABLE BUFFER INPUT Disables ADC inputs to the buffer D 19 R W CLEAR BUFFER Clears...

Page 46: ...DISABLE 2 D 15 12 GROUP 3 ENABLE DISABLE 3 D 31 16 Reserved Table 3 6 1 2 2 Rate Generator Assignment Codes ASSIGNMENT CODE GROUP 0 ASSIGNMENT GROUPS 1 3 ASSIGNMENT 0 Internal Rate Generator Unused 1...

Page 47: ...fset 0008h Default 0000 01F4h BIT FIELD MODE DESIGNATION FUNCTION D 09 00 R W VCO FACTOR Nvco PLL VCO factor 30 1000 D 31 10 R W Reserved Table 3 6 2 1 3 Summary of PLL Sample Rate Control Parameters...

Page 48: ...ady 3 Data Buffer threshold flag LOW to HIGH transition 4 Data Buffer threshold flag HIGH to LOW transition 5 Reserved 6 Reserved 7 Reserved Table 3 9 1 Typical DMA Register Configuration DMA Channel...

Page 49: ...SAMPLE EVENT NON SYNCHRONIZED SCANS Typical SYNCHRONIZED SCANS Tn 34567012 01234567 Tn 1 56701234 01234567 Tn 2 01234567 01234567 Tn 3 45670123 01234567 Tn 4 12345670 01234567 Table 3 11 1 Board Conf...

Page 50: ...pose Although extensive editing and reviews are performed before release to ECO control General Standards Corp assumes no responsibility for any errors that may exist in this document No commitment is...

Page 51: ...General Standards Corporation Ph 256 880 8787 FAX 256 880 8788 Email solutions GeneralStandards com Web Site http www GeneralStandards com MAN PCIe 24DSI32...

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