PCIe-24DSI32
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General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: [email protected]
3-5
3.4.3 Settling Delays and the Channels Ready Flag
When a critical parameter such as input mode or sample rate is changed, a settling transition
occurs during which input measurements are unpredictable.
A settling delay is inserted
automatically when any or all of these parameters are changed, and the CHANNELS READY
status flag in the BCR goes LOW during the delay. A LOW-to-HIGH transition of this flag is
selectable as an interrupt request "channels ready" event (Section 3.8.1). The CHANNELS
READY flag goes low during the following operations for the approximate intervals indicated:
5 Seconds:
Board initialization (3.3),
1 us:
Buffer reset, if not in synchronous-scanning mode (3.5.3.2),
10 us-5 ms:
Buffer reset, if in synchronous-scanning mode (3.5.3.2),
100 ms:
Sample rate change ; i.e.: Nrate, Ndiv, Rate assignments (3.6).
1-100 ms:
ADC synchronization (3.6.5 and 3.10),
1-100 ms:
Synchronous-scan initiation (3.10),
3.5 Input Data Buffer
3.5.1 General Characteristics
Analog input samples accumulate in the analog input data FIFO data buffer, which has a
capacity of 256K (262,144) data values. Data accumulates in the buffer until extracted by the
PCI bus from a single register location, indicated as INPUT DATA BUFFER in Table 3.1.
Reading an empty buffer returns an indeterminate value.
3.5.2 Data Organization
Each value in the data buffer consists of a 5-bit channel tag field, a zero-pad field, and a data
field, as shown in Table 3.5.2. The width of the right-justified data field is adjustable from 16
bits to 24 bits by the buffer control register (Table 3.5.3), and the width of the zero-pad field is
adjusted accordingly. The zero-pad field becomes a sign-extension field if two's complement
data coding is selected.
Table 3.5.2. Input Data Buffer Organization
Offset: 0000 0030h
Default: XXXX XXXXh
SELECTED
DATA WIDTH
RESERVED (Zero)
CHANNEL TAG
ZERO-PAD
CHANNEL DATA VALUE
16 Bits
D[31..29]
D[28..24]
D[23..16]
D[15..0]
18 Bits
D[31..29]
D[28..24]
D[23..18]
D[17..0]
20 Bits
D[31..29]
D[28..24]
D[23..20]
D[19..0]
24 Bits
D[31..29]
D[28..24]
---
D[23..0]
3.5.2.1 Channel Tags
If the input channels are not scan-synchronized (Paragraph 3.10), the order in which channel
data accumulates in the buffer is not generally predictable. Therefore, a channel tag that
identifies each input channel is attached to associated data values in the buffer.
.
