PCIe-24DSI32
_____________________________________________________________________________
General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: [email protected]
3-11
The ADC sample rate
Fsamp
is determined by the rate generator frequency
Fgen
and a rate
DIVISOR
as: (all values in decimal)
(3-1)
where
Fsamp
and
Fgen
are in kilohertz, and
DIVISOR
is defined as:
If Ndiv > 0, then DIVISOR = Ndiv,
If Ndiv = 0, then DIVISOR = 0.5,
(3-2)
where
Ndiv
can have any integer value from zero through 25.
Fgen
has a range of
20 - 55 MHz for the PLL
rate generator
option
, or 25.6 - 51.2 MHz
for the legacy option
. Refer
to Section 3.6.2.
Note: The ADC's operate in one of three different clocking modes, with each mode determined
by the required sample rate. In addition to establishing the sample rate division factor,
the integer
Ndiv
also controls the ADC clocking mode.
3.6.2 Rate Generator Control
The internal rate generator is a PLL-controlled oscillator locked to a stable reference frequency.
Older (Legacy) versions of this product implement a rate generator that could be adjusted with
0.2-percent resolution. The higher-resolution PLL configuration however provides less clock
jitter, and consequently produces a more finely detailed spectrum and a lower noise floor. The
frequencies of the generator is controlled by the Nref and Nvco control registers listed in
Table 3.1. The effect of these registers is determined by the specific PLL or Legacy rate
generator option that is present on the board, which is specified as an ordering option.
3.6.2.1 PLL Rate Generator
If the PLL Rate Generator ordering option applies,
Fgen
is generated by an internal phase-
locked loop (PLL) oscillator with a frequency range of 20-55 MHz. The frequency
Fgen
of the
oscillator is related to a reference frequency
Fref
by integers
Nref
and
Nvco
(Tables 3.6.2.1-1
and 3.6.2.1-2) as:
(3-3)
where
Nvco
and
Nref
each has a maximum range from 30 to 1000, and
Fref
is the frequency
of the reference oscillator, which has a standard frequency of
32.768MHz
. Table 3.6.2.1-3
summarizes the sample rate control parameters.
Fgen
DIVISOR * 512
=
Fsamp
,
Nvco
Nref
=
Fgen
Fref
*
,
