SECTION 3.0
CONTROL SOFTWARE
3.1 Introduction
The PCIe-24DSI32 board is compatible with the PCI Express local bus specification revision
1.0a, and a PLX
tm
PEX8311 adapter controls the one-lane interface.
Configuration-space
registers are initialized internally to support the location of the board on any 32-longword
boundary in memory space.
After initialization, communication between the PCIe bus and the board takes place through the
control and data registers shown in Table 3.1. All data transfers are long-word D32. Reserved
bits in each register are ignored during write operations, and are forced LOW during read
operations.
To ensure compatibility of applications with subsequent product upgrades,
reserved bits should be written as LOW.
Table 3.1. Control and Data Registers
LOCAL
ADDR
ACCESS
MODE
REGISTER
DEFAULT
DESCRIPTION
00
R/W
Board Control (BCR)
0000 383Ch *
Board Control Register (BCR)
04
R/W
Nref PLL Control
0000 01F4h
PLL reference oscillator control integer.
(PLL configuration only)
08
R/W
Nvco PLL Control
(Legacy Nrate)
0000 01F4h
PLL vco control integer.
(Nrate for the legacy rate generator)
0C
R/W
Rate Assignments
0000 0000h ****
ADC Clock source; Group disables.
10
R/W
Rate Divisor
0000 0005h
Sample rate divisor.
14
RO
(Reserved)
0000 0000h
---
18
R/W
PLL Reference Freq
XXXX XXXX
h
PLL reference frequency indicator
1C
RO
(Reserved)
0000 0000h
---
20
R/W
Buffer Control
0X03 FFFEh **
Input buffer control and status
24
RO
Board Configuration
00
XX XXXX
h
Installed firmware and hardware options
28
RO
Buffer Size
0
XXX XXXX
h
Number of ADC values in the input buffer.
2C
RO
Autocal Values ***
---
---
30
RO (DMA)
Input Data Buffer
XXXX XXXX
h
Input Data Buffer; Data and channel tag
34-7C
--
(Reserved)
---
---
* Changes to 0000 783Ch when the input buffer fills.
** Changes to 0103 FFFEh when the buffer fills.
*** Maintenance register. Shown for reference only.
**** May be 0000 0190h in earlier firmware revisions.
