PCIe-24DSI32
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General Standards Corporation Ph:(256)880-8787 FAX:(256)880-8788 Email: [email protected]
1-2
1.2 Functional Overview
A PCI Express interface adapter provides the interface between the controlling bus and the
internal local controller through a 32-bit local bus (Figure 1.2). Inputs are organized into
four channel groups, three of which can be designated as either active or inactive
independently of the other groups. Each input channel consists of configuration switches
for selftest and autocalibration operations, as well as range-scaling and analog image filter
networks. Each even-odd channel pair also contains a dual delta-sigma A/D converter
(ADC) that provides two separate but synchronized conversion channels.
An internal
voltage reference can be applied to all channels to support selftest operations and
autocalibration. Gain and offset trimming of the input channels is performed by applying
correction values obtained during autocalibration.
PCI
Conn
I/O
Conn
Analog
Inputs
(32 Diff)
Input
Configuration
Switches
PCI
Interface
Adapter
Local
Controller
Voltage
Reference
To ADC’S
Sample-Rate
Generator
Scaling
& Filters
Input
Data
24-Bit ADC’s
(32)
External
Sync
Input
Control
Local Bus
Figure 1.2. Functional Organization
An internal sample-rate clock generator is adjustable from 20 MHz to 55 MHz, and is
divided down within the local controller to provide sample rates from 2.0 KSPS to
200 KSPS. Input bandwidth varies from 1000 Hz to 80 kHz, depending upon the selected
sample rate, and extends down to DC.
Conversion data from all active channels is
transferred to the PCI bus through a 256K-sample FIFO data buffer.
Multiple channels can be synchronized to perform sampling in "lockstep", either by a
software command, or by external hardware sync and clock input signals. Hardware sync
and clock input/output signals permit multiple boards to be connected together for phase-
locked operation from a common clock.
