General Standards Corporation PCIe-24DSI32, Reference Manual

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PCIe-24DSI32
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A-3
Table 3.2. Board Control Register
Offset: 0000h Default: 0000 383Ch **
DATA BIT MODE DESIGNATION DESCRIPTION
D00 R/W AIM0 Analog input mode. Selects system inputs or
D01 R/W AIM1 selftest mode. Defaults to system inputs.
D02 R/W RANGE0 Analog input range selection. Defaults to ±10V range.
D03 R/W RANGE1
D04 R/W OFFSET BINARY
Selects offset binary or two's complement input data
format. Defaults HIGH to offset binary.
D05 R/W INITIATOR
Selects INITIATOR or TARGET mode for external clock
and sync signals. Defaults HIGH to Initiator mode.
D06 R/W *SOFTWARE SYNC
Initiates a local ADC sync operation when asserted.
Also generates an external sync output if INITIATOR
mode is selected. Clears automatically.
D07 R/W *AUTOCAL
Initiates an autocalibration operation when asserted.
Clears automatically upon autocal completion.
D08 R/W INTERRUPT A0 Interrupt event selection. Default is zero.
D09 R/W INTERRUPT A1
D10 R/W INTERRUPT A2
D11 R/W INTERRUPT REQUEST FLAG
Set HIGH when the
board
requests an interrupt.
Clears the request when cleared LOW by the bus.
D12 RO AUTOCAL PASS
Set HIGH at reset or autocal initialization. Cleared
LOW if autocalibration terminates unsuccessfully.
D13 RO CHANNELS READY
LOW during any change in channel parameters.
Asserted HIGH when inputs are ready to acquire data.
D14 RO BUFFER THRESHOLD FLAG
Asserted HIGH when buffer contents exceed the
assigned threshold.
D15 R/W *INITIALIZE Initializes the board when asserted. Sets all defaults.
D16 R/W SYNCHRONIZE SCAN Selects synchronous sampling mode.
D17 R/W CLEAR BUFFER ON SYNC
When this bit is HIGH, the context of the SOFTWARE
SYNC control bit changes to CLEAR BUFFER.
D18 R/W
RATE GEN EXT CLOCK OUT
(Initiator Mode only)
When HIGH:
Selects the internal rate generator as the external
clock output source.
When LOW:
Selects the Group-00 sample clock. (If Group-00
external clocking is selected, the output is driven by
the internal rate generator and the Group-00
divisor).
D19 R/W SELECT LOW IMAGE FILTER
When this bit is HIGH, the low-frequency image filter is
selected. When LOW, the high filter is selected.
D20 R/W (Reserved) --
D21 R/W ARM EXTERNAL TRIGGER Arms the external burst trigger input. (3.12)
D22 R/W THRESHOLD FLAG OUT Routes the threshold flag to the AUX LVDS output.
D23-31 RO (Reserved) ---
* Cleared automatically. R/W = Read/Write; RO = Read-Only.
** Changes to 0000 783Ch when the input buffer fills.