PCIe-24DSI32
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3-7
NOTE: Since delta-sigma ADC's perform conversions continuously, the initiation and
termination of acquisition sequences is controlled by the buffer's 'Clear' and
'Disable' controls.
3.5.3.1 Status Flag and Threshold
The amount of data contained in the input buffer can be used to control the BUFFER
THRESHOLD FLAG status bit, which can be selected as an interrupt request event. The
interrupt request event can be selected to occur on either the rising or falling edge of the flag
(Table 3.8.1).
The threshold flag is asserted HIGH when the number of samples in the buffer
exceeds
the
BUFFER THRESHOLD value in the buffer control register. A buffer-empty event is produced
when the threshold value is adjusted to equal 0000 0000h and the threshold flag undergoes a
HIGH-to-LOW transition.
NOTE: Effective in firmware revision 0502 and subsequent 05XX revisions, the
THRESHOLD FLAG OUT control bit is active in the BCR. When this bit is set
HIGH, the threshold flag is routed to the AUX LVDS OUT output in the system I/O
connector.
3.5.3.2 Buffer Clearing and Disabling
Asserting the CLEAR BUFFER control bit in the buffer control register resets (empties) the
buffer, and holds the buffer in reset until the internal data pipeline clears, approximately 1.0
microsecond. This bit clears automatically.
Asserting the DISABLE BUFFER INPUT control bit disables inputs to the buffer from the ADC
input channels, and halts the accumulation of further input data. Input data already present in
the buffer when this bit is asserted remains in the buffer.
Note: The buffer also can be cleared by writing a "one" to the SOFTWARE SYNC control bit in
the BCR when the CLEAR BUFFER ON SYNC control bit is HIGH. See "Global Buffer
Clear" in Paragraph 3.10.
3.5.4 Buffer Size Register
This read-only register contains the number of analog input values currently stored in the input
data buffer.
3.5.5 Buffer Underflow and Overflow Flags
BUFFER OVERFLOW and BUFFER UNDERFLOW status bits in the buffer control register
report overflow (write on full) or underflow (read on empty) events. Once set, these status bits
remain HIGH until cleared by writing LOW directly, or by a board reset.
