PCIe-24DSI32
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3-20
3.10 Scan Synchronization
Although the data sequence for any specific channel in the data buffer represents the actual
sampling sequence for that channel, the ordering of multiple channels in the buffer can vary
due to the asynchronous nature of the sample clock relative to the board's master clock. These
variations in channel order can occur even though all channels are synchronized to a common
sample clock.
Variations in the ordering of multiple channels can be eliminated by synchronizing the
acquisition of each scan to the board's master clock. This
scan-synchronization
can be
effective only if all active channels are operating from a common clock source.
Note: References to
channel synchronization
in this manual pertain to the situation in which
the sampling of all input channels occurs simultaneously.
Scan-synchronization
refers
to the synchronization of discrete data scans to the master clock, to ensure a
consistent ordering of data channels in the data buffer.
For synchronized scans, the channel sequence for each scan in the buffer is ordered from
lowest to highest. All samples in each scan represent the same sample event, and are
arranged beginning with the lowest active channel and proceeding upward through the highest
active channel. Table 3.10.1 illustrates examples of channel sequences in both synchronized
and nonsynchronized scans in which eight channels are active. Scan synchronization is
invoked by setting the SYNCHRONIZE SCAN control bit HIGH in the BCR.
Table 3.10.1. Channel Order (Active channels 00-07)
CHANNEL ORDER
SAMPLE EVENT
NON-SYNCHRONIZED
SCANS (Typical)
SYNCHRONIZED SCANS
Tn
34567012
01234567
Tn+1
56701234
01234567
Tn+2
01234567
01234567
Tn+3
45670123
01234567
Tn+4
12345670
01234567
