PACE Series SCPI Manual
K0472 Revision A
3 - 5
3.3
Operation status group
The operation status group are 16 bit registers that are read by the STAT:OPER:PRES
commands. The event register is cleared by reading it; the event and enable registers are
cleared by the *CLS command.
When a standard operation condition occurs an appropriate bit is set in the condition register
(this clears when the condition no longer exists). The bit is then latched in the event register. If
the associated bit in the enable register is set, the OPR bit in the status byte sets. The enable
register may be set through the STAT:OPER:PRES:ENAB command so that only selected standard
operation events cause the OPR bit to set.
Problems can occur with some IEEE 488 controllers reading 16 bit unsigned numbers. All
registers in this group do not use bit 15. The enable bit cannot be set and when read returns 0.
The condition register is defined as follows:
Vent complete
This signal occurs when the controller has been requested to vent and the vent has
completed or timed out.
Range change complete
This signal occurs when the controller has been requested to perform a range change and
the range change is complete.
In-Limits reached
This signal is set every time the controlled pressure is within the specified limits. The signal is
only generated if the pressure has been within limits for a user defined wait time period.
Zero complete
This signal is generated when a manual or timed zero is complete. If the zero times out then
this signal is also generated.
Range compare alarm (PACE1000 only)
This signal is generated when the range compare alarm is triggered during the range
compare process.
