Freescale Semiconductor MCF5329, Reference Manual, Page: 77 / 924

ColdFire Core
Freescale Semiconductor 3-3
• Two-stage operand execution pipeline (OEP)
— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the
required components for effective address calculation, or the operand fetch cycle
— Address generation/execute cycle (AGEX)—Calculates operand address or executes the
instruction
When the instruction buffer is empty, opcodes are loaded directly from the IED cycle into the operand
execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetched instruction and its
early decode informration in the IB until it is required by the OEP.
For register-to-register and register-to-memory store operations, the instruction passes through both OEP
stages once. For memory-to-register and read-modify-write memory operations, an instruction is
effectively staged through the OEP twice: the first time to calculate the effective address and initiate the
operand fetch on the processor’s local bus, and the second time to complete the operand reference and
perform the required function defined by the instruction.
The V3 ColdFire core’s instruction buffer is organized differently than the V2 ColdFire core’s. One of the
time-critical decode fields provided by the early-decode stage of the IFP is the instruction length. By
knowing the length of the prefetched instructions, the IED field can package the fetched data into machine
instructions and load them into the FIFO instruction buffer in that form. This approach greatly simplifies
and accelerates the OEP read logic. As one instruction is completed in the OEP, the next
instruction—regardless of instruction length—is read from the next sequential buffer location and loaded
into the instruction registers.
The resulting pipeline and local bus structure allow the V3 ColdFire core to deliver sustained high
performance across a variety of demanding embedded applications.
3.1.1.1 Change-of-Flow Acceleration
Because the IFP and OEP are decoupled by the instruction buffer, the increased depth of the IFP is
generally hidden from the OEP’s instruction execution. However, for change-of-flow instructions, such as
unconditional branches or jumps, subroutine calls, taken conditional branches, the increased IFP depth is
fully exposed. To minimize the effects of this increased depth, a logic module dedicated to change-of-flow
acceleration was developed for the IED stage of the IFP.
The basic premise of the V3 ColdFire core’s branch acceleration is to detect certain types of
change-of-flow instructions, calculate their target instruction address, and immediately begin fetching
down the target stream. By allowing the IFP to manage switching of the prefetch stream without OEP
intervention, typical execution time is greatly improved.
For example, consider a PC-relative unconditional branch using the BRA instruction. The branch
acceleration logic searches the prefetch stream for this type of opcode. After encountered, the acceleration
logic calculates the target address by summing the current instruction prefetch address with a displacement
contained in the instruction. This detection and calculation of the target address occurs in the IED stage of
the BRA prefetch. The target address is then immediately fed back into the IAG stage, causing the current
prefetch stream to be discarded and establishing a new stream at the target address. Given that the two
pipelines are decoupled, in many cases, the target instruction is available to the OEP immediately after the
BRA instruction, making its execution time appear as a single cycle.
MCF5329 Reference Manual, Rev 3