Freescale Semiconductor MCF5329, Reference Manual, Page: 637 / 924

Synchronous Serial Interface (SSI)
Freescale Semiconductor 24-43
• Slot 2: If WR command, command data
• Slot 3–12: Transmit FIFO data, depending on the valid slots indicated by the TAG value
While receiving, bit 15 of the received tag slot (slot 0) is checked to see if the codec is ready. If this bit is
set, the frame is received. The received tag provides the information about slots containing valid data. If
the corresponding tag bit is valid, the command address (slot 1) and command data (slot 2) vaules are
stored in the corresponding registers. The received data (slot 3–12) is then stored in the receive FIFO (for
valid slots).
24.4.1.5.2 AC97 Variable Mode (SSI_ACR[FV]=1)
In variable mode, the transmit slots that should contain data in the current frame are determined by the
SLOTREQ bits received in slot 1 of the previous frame. While receiving, if the codec is ready, the frame
is received and the SLOTREQ bits are stored for scheduling transmission in the next frame.
The SACCST, SACCEN and SACCDIS registers help determine which transmit slots are active. This
information is used to ensure that SSI does not transmit data for powered-down/inactive channels.
24.4.2 SSI Clocking
The SSI uses the following clocks:
• SSI_CLOCK — This is the internal clock that drives the SSI’s clock generation logic, which can
be a fraction of the internal core clock (f
sys
) or the clock input on the SSI_CLKIN pin. The CCM’s
MISCCR register can select either of these sources. Having this choice allows the user to operate
the SSI module at frequencies that would not be achievable if standard internal core clock
frequencies (180 or 240 MHz) are used. This is also the output master clock (SSI_MCLK) when
in master mode.
• Bit clock — Serially clocks the data bits in and out of the SSI port. This clock is generated
internally or taken from external clock source (through SSI_BCLK).
• Word clock — Counts the number of data bits per word (8, 10, 12, 16, 18, 20, 22 or 24 bits). This
clock is generated internally from the bit clock.
• Frame clock (frame sync) — Counts the number of words in a frame. This signal can be generated
internally from the bit clock or taken from external source (from SSI_FS).
• Master clock — In master mode, this is an integer multiple of frame clock. It is used in cases when
SSI has to provide a clock to the connected devices.
Take care to ensure that the bit clock frequency (internally generated or sourced from an external device)
is never greater than 1/5 of the internal bus frequency (f
sys/3
).
In normal mode, the bit clock, used to serially clock the data, is visible on the serial clock (SSI_BCLK)
port. The word clock is an internal clock that determines when transmission of an 8, 10, 12, 16, 18, 20, 22,
or 24-bit word has completed. The word clock then clocks the frame clock, which counts the number of
words in the frame. The frame clock can be viewed on the SSI_FS frame sync port because a frame sync
generates after the correct number of words in the frame have passed. In master mode, the SSI_MCLK
signal is the serial master clock if enabled by the SSI_CR[MCE] bit. This serial master clock is an
oversampling clock of the frame sync clock (SSI_FS). In this mode, the word length (WL), prescaler range
MCF5329 Reference Manual, Rev 3