Freescale Semiconductor MCF5329, Reference Manual, Page: 383 / 924

SDRAM Controller (SDRAMC)
Freescale Semiconductor 18-21
Any chip-select can be enabled or disabled, independent of others. Any chip-select can be allocated any
size of address space from 1M to 4G, independent of others. Any chip-select address space can begin at
any size-aligned base address, independent of others.
For contiguous memory with different sizes of memory blocks, place largest block at the lowest address
and place smaller blocks in descending size order at ascending base addresses.
For example, assume a system with 2 chip selects: CS0=16M, CS1=256M:
CS0CFG = 0x4F000017 = enable 16M @ 0x4F000000-0x4FFFFFFF
CS1CFG = 0x5000001B = enable 256M @ 0x50000000-0x5FFFFFFF
This gives 272 MB total memory, at 0x4F000000-0x5FFFFFFF.
18.5 Functional Description
18.5.1 SDRAM Commands
When an internal bus master accesses SDRAM address space, the memory controller generates the
corresponding SDRAM command.
Table 18-12 lists SDRAM commands supported by the memory
controller.
Table 18-11. SDCSn Field Descriptions
Field Description
31–20
CSBA Chip-select base address. Because the SDRAM module is one of the slaves connected to the crossbar switch, it is
only accessible within a certain memory range. The only applicable address ranges for which the chip-selects can
be active are 0x4000_0000 – 0x7FFF_FFFF. Therefore, the possible range for this field is 0x400 – 0x7FF.
19–5 Reserved, must be cleared.
4–0
CSSZ
Chip select size.
CSSZ Size
Address Lines
to Compare
CSSZ Size
Address Lines
to Compare
00000 Disabled — 11000 32 MByte A[31:25]
00001–10001 Reserved Reserved 11001 64 MByte A[31:26]
10010 Reserved Reserved 11010 128 MByte A[31:27]
10011 1 MByte A[31:20] 11011 256 MByte A[31:28]
10100 2 MByte A[31:21] 11100 512 MByte A[31:29]
10101 4 MByte A[31:22] 11101 1 GByte A[31:30]
10110 8 MByte A[31:23] 11110 2 GByte A31
10111 16 MByte A[31:24] 11111 4 GByte Ignore A[31:20]
MCF5329 Reference Manual, Rev 3