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Freescale Semiconductor MCF5329 Reference Manual Download Page 372

SDRAM Controller (SDRAMC)

18-10

Freescale Semiconductor

For 32-bit data bus configuration:

•

If all devices’ row address width is 12 bits, the column address can be

≥

8 bits.

•

If all devices’ row address width is 13 bits, the column address can be

≥

8 bits.

•

If all devices’ column address width is 8 bits, the row address can be

≥

11 bits.

•

The maximum row bits plus column bits equals 24.

•

x8 and x16 data width memory devices can be mixed (but not in the same space).

•

x32 data width memory devices cannot be mixed with any other width.

For 16-bit data bus configuration:

•

If all devices’ row address width is 12 bits, the column address can be

≥

9 bits.

•

If all devices’ row address width is 13 bits, the column address can be

≥

9 bits.

•

If all devices’ column address width is 9 bits, the row address can be

≥

11 bits.

•

The maximum row bits plus column bits equals 25.

•

x16 data width memory devices cannot be mixed with any other width.

18.3.2

SDRAM SDR Connections

shows a block diagram using 32-bit wide SDR SDRAM (such as Micron MT48LC4M32B2)

and flash (such as Spansion AM29LV160D). SDR design requires special timing consideration for the
SD_DQS[3: ] signals. For reads from DDR SDRAMs, the memory drives the DQS pins so that the data
lines and DQS signals have concurrent edges. The SDRAMC is designed to latch data 1/4 clock after the
SD_DQS[3: ] edge. For DDR SDRAM, this ensures that the latch time is in the middle of the data valid
window.

The SDRAMC also uses the SD_DQS[3: ] signals to determine when read data can be latched for SDR
SDRAM; however, SDR memories do not provide DQS outputs. Instead the SDRAMC provides a
SD_SDRDQS output routed back into the controller as SD_DQS[3: ]. The SD_SDRDQS signal should
be routed such that the valid data from the SDRAM reaches the controller at the same time or before the
SD_SDRDQS reaches the SD_DQS[3: ] inputs.

When routing SD_SDRDQS the outbound trace length should be matched to the SD_CLK trace length.
This aligns SD_SDRDQS to the SD_CLK as if the memory had generated the DQS pulse. The inbound
trace should be routed along the data path, which should synchronize the SD_DQS so that the data is
latched in the middle of the data valid window.

2

2

2

2

2

MCF5329 Reference Manual, Rev 3

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Summary of Contents for MCF5329

Page 1: ...MCF5329 Reference Manual Devices Supported MCF5327 MCF5328 MCF53281 MCF5329 Document Number MCF5329RM Rev 3 12 2008...

Page 2: ...particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including wit...

Page 3: ...ule Universal Serial Bus Interface On The Go Module Liquid Crystal Display Controller LCDC FlexCAN Synchronous Serial Interface SSI Real Time Clock Pulse Width Modulation PWM Module Watchdog Timer Mod...

Page 4: ...nterface Host Module Universal Serial Bus Interface On The Go Module Liquid Crystal Display Controller LCDC FlexCAN Synchronous Serial Interface SSI Real Time Clock Pulse Width Modulation PWM Module W...

Page 5: ...Features 1 3 1 3 1 V3 Core Overview 1 8 1 3 2 Debug Module 1 9 1 3 3 JTAG 1 9 1 3 4 On chip Memories 1 9 1 3 5 LCD Controller 1 10 1 3 6 Voice over IP VoIP System Solution 1 10 1 3 7 SDR DDR SDRAM Con...

Page 6: ...2 9 2 3 2 PLL and Clock Signals 2 9 2 3 3 Mode Selection 2 10 2 3 4 FlexBus Signals 2 11 2 3 5 SDRAM Controller Signals 2 12 2 3 6 External Interrupt Signals 2 12 2 3 7 DMA Signals 2 12 2 3 8 LCD Cont...

Page 7: ...nctional Description 3 10 3 3 1 Version 3 ColdFire Microarchitecture 3 10 3 3 2 Instruction Set Architecture ISA_A 3 11 3 3 3 Exception Processing Overview 3 12 3 3 4 Processor Exceptions 3 15 3 3 5 I...

Page 8: ...3 6 Cache Coherency 5 13 5 3 7 Memory Accesses for Cache Maintenance 5 13 5 3 8 Cache Locking 5 15 5 3 9 Cache Management 5 16 5 3 10 Cache Operation Summary 5 17 Chapter 6 Static RAM SRAM 6 1 Introdu...

Page 9: ...Wake up Control Register 8 2 8 2 2 Peripheral Power Management Set Registers PPMSR0 PPMSR1 8 3 8 2 3 Peripheral Power Management Clear Registers PPMCR0 PPMCR1 8 4 8 2 4 Peripheral Power Management Re...

Page 10: ...Selection 9 11 9 4 5 Output Pad Strength Configuration 9 11 9 4 6 Chip Select Configuration 9 12 Chapter 10 Reset Controller Module 10 1 Introduction 10 1 10 1 1 Block Diagram 10 1 10 1 2 Features 10...

Page 11: ...ore Fault Data Register CFDTR 11 13 11 3 Functional Description 11 14 11 3 1 Access Control 11 14 11 3 2 Core Watchdog Timer 11 14 11 3 3 Core Data Fault Recovery Registers 11 15 Chapter 12 Crossbar S...

Page 12: ...RHn IPRLn 14 4 14 2 2 Interrupt Mask Register IMRHn IMRLn 14 5 14 2 3 Interrupt Force Registers INTFRCHn INTFRCLn 14 6 14 2 4 Interrupt Configuration Register ICONFIG 14 7 14 2 5 Set Interrupt Mask Re...

Page 13: ..._ES 16 5 16 6 3 eDMA Enable Request Register EDMA_ERQ 16 8 16 6 4 eDMA Enable Error Interrupt Registers EDMA_EEI 16 9 16 6 5 eDMA Set Enable Request Register EDMA_SERQ 16 9 16 6 6 eDMA Clear Enable Re...

Page 14: ...FB_BE BWE 3 0 17 3 17 2 4 Output Enable FB_OE 17 3 17 2 5 Read Write FB_R W 17 3 17 2 6 Transfer Start FB_TS 17 3 17 2 7 Transfer Acknowledge FB_TA 17 3 17 3 Memory Map Register Definition 17 4 17 3...

Page 15: ...Configuration Registers SDCSn 18 20 18 5 Functional Description 18 21 18 5 1 SDRAM Commands 18 21 18 5 2 Read Clock Recovery RCR Block 18 26 18 6 Initialization Application Information 18 27 18 6 1 Pa...

Page 16: ...19 4 20 FIFO Receive Bound Register FRBR 19 22 19 4 21 FIFO Receive Start Register FRSR 19 22 19 4 22 Receive Descriptor Ring Start Register ERDSR 19 23 19 4 23 Transmit Buffer Descriptor Ring Start...

Page 17: ...cription 21 5 21 2 1 USB OTG Control and Status Signals 21 6 21 3 Memory Map Register Definition 21 8 21 3 1 Module Identification Registers 21 9 21 3 2 Capability Registers 21 13 21 3 3 Operational R...

Page 18: ...ster LCD_RMCR 22 17 22 3 15 LCDC Interrupt Configuration Register LCD_ICR 22 18 22 3 16 LCDC Interrupt Enable Register LCD_IER 22 19 22 3 17 LCDC Interrupt Status Register LCD_ISR 22 20 22 3 18 LCDC G...

Page 19: ...23 13 23 3 7 Interrupt Mask Register IMASK 23 15 23 3 8 Interrupt Flag Register IFLAG 23 16 23 3 9 Message Buffer Structure 23 16 23 3 10 Functional Overview 23 20 23 3 11 Transmit Process 23 20 23 3...

Page 20: ...ive Configuration Register SSI_RCR 24 23 24 3 12 SSI Clock Control Register SSI_CCR 24 24 24 3 13 SSI FIFO Control Status Register SSI_FCSR 24 25 24 3 14 SSI AC97 Control Register SSI_ACR 24 27 24 3 1...

Page 21: ...10 25 4 3 Sampling Timer 25 11 25 4 4 Minute Stopwatch 25 11 25 5 Initialization Application Information 25 12 25 5 1 Flow Chart of RTC Operation 25 12 25 5 2 Programming the Alarm or Time of Day Reg...

Page 22: ...upt Timers PIT0 PIT3 28 1 Introduction 28 1 28 1 1 Overview 28 1 28 1 2 Block Diagram 28 1 28 1 3 Low Power Mode Operation 28 1 28 2 Memory Map Register Definition 28 2 28 2 1 PIT Control and Status R...

Page 23: ...9 10 Chapter 30 Queued Serial Peripheral Interface QSPI 30 1 Introduction 30 1 30 1 1 Block Diagram 30 1 30 1 2 Overview 30 2 30 1 3 Features 30 2 30 1 4 Modes of Operation 30 2 30 2 External Signal D...

Page 24: ...31 3 10 UART Interrupt Status Mask Registers UISRn UIMRn 31 13 31 3 11 UART Baud Rate Generator Registers UBG1n UBG2n 31 15 31 3 12 UART Input Port Register UIPn 31 15 31 3 13 UART Output Port Command...

Page 25: ...32 12 32 4 3 Post Transfer Software Response 32 13 32 4 4 Generation of STOP 32 13 32 4 5 Generation of Repeated START 32 14 32 4 6 Slave Mode 32 14 32 4 7 Arbitration Lost 32 14 Chapter 33 Message Di...

Page 26: ...34 1 34 2 Memory Map Register Definition 34 2 34 2 1 RNG Control Register RNGCR 34 2 34 2 2 RNG Status Register RNGSR 34 3 34 2 3 RNG Entropy Register RNGER 34 4 34 2 4 RNG Output FIFO RNGOUT 34 4 34...

Page 27: ...iagram 36 1 36 1 2 Overview 36 1 36 2 Signal Descriptions 36 2 36 3 Memory Map Register Definition 36 3 36 3 1 Shared Debug Resources 36 4 36 3 2 Configuration Status Register CSR 36 5 36 3 3 BDM Addr...

Page 28: ...TDO DSO 37 4 37 3 Memory Map Register Definition 37 4 37 3 1 Instruction Shift Register IR 37 4 37 3 2 IDCODE Register 37 5 37 3 3 Bypass Register 37 5 37 3 4 TEST_CTRL Register 37 5 37 3 5 Boundary S...

Page 29: ...of Chapter 20 Universal Serial Bus Interface Host Module and Chapter 21 Universal Serial Bus Interface On The Go Module relating to the EHCI specification are Copyright Intel Corporation 1999 2001 Th...

Page 30: ...device s different clocking methods It also describes clock module operation in low power modes Chapter 8 Power Management describes the low power operation of the device and peripheral behavior in l...

Page 31: ...2 0 is a recommended supplement to this chapter Chapter 21 Universal Serial Bus Interface On The Go Module provides an overview of the universal serial bus USB On the Go module The USB Specification...

Page 32: ...application information Chapter 35 Symmetric Key Hardware Accelerator SKHA describes the cryptographic hardware coprocessor designed to implement two widely used symmetric key block cipher algorithms...

Page 33: ...hat describes the additional features and functionality changes Also if mistakes are found within a reference manual an errata document will be issued before the next published release of the referenc...

Page 34: ...don t care n Used to express an undefined numerical value NOT logical operator AND logical operator OR logical operator OVERBAR An overbar indicates that a signal is active low Register Figure Convent...

Page 35: ...ELDNAME Table 1 Acronyms and Abbreviated Terms Term Meaning ADC Analog to digital conversion ALU Arithmetic logic unit BDM Background debug mode BIST Built in self test BSDL Boundary scan description...

Page 36: ...on OEP Operand execution pipeline PC Program counter PCLK Processor clock PLIC Physical layer interface controller PLL Phase locked loop POR Power on reset PQFP Plastic quad flat pack PWM Pulse width...

Page 37: ...register i can be an address or data register Ai Di Miscellaneous Operands data Immediate data following the 16 bit operation word of the instruction ea Effective address ea y ea x Source and destina...

Page 38: ...dition If true the operations after then are performed If the condition is false and the optional else clause is present the operations after else are performed If the condition is false and else is o...

Page 39: ...cessors It was written from the perspective of the MCF5329 device See the following section for a summary of differences between the devices 1 1 MCF532x Device Configurations The following table compa...

Page 40: ...Real Time Clock 32 bit DMA Timers 4 4 4 4 Watchdog Timer WDT Periodic Interrupt Timers PIT 4 4 4 4 Edge Port Module EPORT Interrupt Controllers INTC 2 2 2 2 16 channel Direct Memory Access DMA FlexBu...

Page 41: ...r 48 bit accumulators to support 32 bit signal processing algorithms FlexBus XBS M2 M1 M0 M5 PWMs EPORT JTAG TAP TRST TCLK TMS TDI TDO Cache 1024x32 x4 DMA UARTs FlexCAN I2C QSPI DMA Timers Watchdog P...

Page 42: ...s and self refresh type LCD panels 16 simultaneous gray scale levels from a palette of 16 for monochrome display Maximum supported panel size of 800x600 pixels 4 mapped to RGB444 8 RGB444 12 bits per...

Page 43: ...s Revision 1 0 Uses 60 MHz reference clock based on the system clock or from an external pin Synchronous serial interface SSI Supports shared synchronous transmit and receive sections Normal mode oper...

Page 44: ...p bits in 1 16 increments Error detection capabilities Flow control support includes request to send UnRTS and clear to send UnCTS lines I2 C module Interchip bus interface for EEPROMs A D converters...

Page 45: ...Support for up to 126 interrupt sources Unique vector number for each interrupt source Ability to mask any individual interrupt source or all interrupt sources global mask all Support for hardware an...

Page 46: ...peline IFP is responsible for instruction address generation and instruction fetch The instruction buffer is a first in first out FIFO buffer that holds prefetched instructions awaiting execution in t...

Page 47: ...debug module provides processor status PST 3 0 and debug data DDATA 3 0 ports These buses and the PSTCLK output provide execution status captured operand data and branch target addresses defining proc...

Page 48: ...mes where the processor and a bus mastering device operate in alternate regions of the SRAM to maximize system performance As an example system performance can be increased significantly if Ethernet p...

Page 49: ...ompliant with the EHCI driver model and support directly connected full speed and low speed devices without the need for UHCI OHCI companion controllers and associated driver stacks Both USB controlle...

Page 50: ...ecification Revision 1 0 1 3 9 Synchronous Serial Interface SSI The SSI is a full duplex serial port that allows the chip to communicate with a variety of serial devices including audio codecs digital...

Page 51: ...vention between transfers 1 3 16 Pulse Width Modulation PWM Timer The pulse width modulation PWM timer generates a synchronous series of pulses having programmable duty cycle With a suitable low pass...

Page 52: ...eform are register programmable The system operates via two main clocks generated by the PLL typically 240 MHz core and 80 MHz peripherals However two additional clocks are also generated by the PLL f...

Page 53: ...signals suitable for use with most popular static RAMs and peripherals Data bus width 8 bit 16 bit or 32 bit is programmable on all chip selects and further decoding is available for protection from u...

Page 54: ...tion Documentation is available from a local Freescale distributor a Freescale sales office the Freescale Literature Distribution Center or through the Freescale World Wide Web address at http www fre...

Page 55: ...with an overbar 2 2 Signal Properties Summary The below table lists the signals grouped by functionality NOTE In this table and throughout this document a single signal within a group is designated wi...

Page 56: ...A 9 0 SD_A 9 0 3 O SDVDD D14 E11 14 F11 F14 G14 E14 E16 F13 F16 G16 G14 E14 E16 F13 F16 G16 G14 D 31 16 SD_D 31 16 4 I O SDVDD H3 H1 J4 J1 K1 L4 M2 M3 N1 N2 P1 P2 N3 M1 M4 N1 N4 T3 P4 R4 T4 N5 P5 R5...

Page 57: ...L1 L1 SD_DQS2 O SDVDD K6 T6 T6 SD_SCAS O SDVDD L3 P3 P3 SD_SRAS O SDVDD M1 R3 R3 SD_SDR_DQS O SDVDD K4 P1 P1 SD_WE O SDVDD D1 H3 H3 External Interrupts Port5 IRQ72 PIRQ72 I EVDD J13 J13 J13 IRQ62 PIR...

Page 58: ...TA 7 5 I EVDD E7 A6 B6 E7 A6 B6 FEC_RXER PFECL0 I EVDD D4 D4 LCD Controller LCD_D17 PLCDDH1 CANTX O EVDD C9 LCD_D16 PLCDDH0 CANRX O EVDD D9 LCD_D17 PLCDDH1 O EVDD A6 C9 LCD_D16 PLCDDH0 O EVDD B6 D9 LC...

Page 59: ...USB VDD H13 L16 L16 USBHOST_M I O USB VDD K13 M15 M15 USBHOST_P I O USB VDD J12 M16 M16 FlexCAN MCF53281 MCF5329 only CANRX and CANTX do not have dedicated bond pads Please refer to the following pin...

Page 60: ...PQSPI4 PWM7 USBOTG_ PU_EN O EVDD L11 T13 T13 QSPI_CS0 PQSPI3 PWM5 O EVDD P11 P11 QSPI_CLK PQSPI2 I2C_SCL2 O EVDD N10 R12 R12 QSPI_DIN PQSPI1 U2CTS I EVDD L10 N12 N12 QSPI_DOUT PQSPI0 I2C_SDA O EVDD M...

Page 61: ...PST 3 0 O EVDD N8 P8 L9 M9 R10 T10 R11 T11 R10 T10 R11 T11 Test TEST7 I EVDD E10 A16 A16 PLL_TEST8 I EVDD N13 N13 Power Supplies EVDD E6 E7 F5 F7 H9 J8 J9 K8 K9 K11 E8 F5 F8 G5 G6 H5 H6 J11 K11 K12 L...

Page 62: ...t responsible for assigning these pins 5 GPIO functionality is determined by the edge port module The GPIO module is only responsible for assigning the alternate functions 6 If JTAG_EN is asserted the...

Page 63: ...red by the MISCCR register in the CCM SSI_RXD x x SSI mode only Configured by the MISCCR register in the CCM SSI_TXD x x SSI mode only Configured by the MISCCR register in the CCM JTAG_EN x TDI x JTAG...

Page 64: ...n USBCLKIN Allows the user to drive the reference clock to the USB modules instead of the clock being generated internally by the PLL This pin should only be driven with a 60 MHz clock When using the...

Page 65: ...ls access to the least significant byte lane of data For SRAM or Flash devices the BE BWEn outputs should be connected to individual byte strobe signals The BE BWEn signals are asserted during accesse...

Page 66: ...determine which byte lanes of the data bus should be latched during a write cycle These pins are multiplexed with the BE BWEn pins The SD_DQMn should be connected to individual SDRAM DQM signals Most...

Page 67: ...Active matrix Output enable to enable data to be shifted onto the display O Contrast LCD_CONTRAST Controls the LCD bias voltage for contrast control O Power Save LCD_PS Controls signal output for sou...

Page 68: ...erted for one or more clock cycles while FEC_TXEN is also asserted the PHY sends one or more illegal symbols FEC_TXER has no effect at 10 Mbps or when FEC_TXEN is negated Applies to MII mode operation...

Page 69: ...t data output O FlexCAN Receive CANRX Controller area network receive data input I Table 2 14 Queued Serial Peripheral Interface QSPI Signals Signal Name Abbreviation Function I O QSPI Syncrhonous Ser...

Page 70: ...viation Function I O On the Go D USBOTG_DM D output of the dual speed transceiver for the On the Go module O On the Go D USBOTG_DP D output of the dual speed transceiver for the On the Go module O On...

Page 71: ...ansmit Serial Data Output UnTXD Transmitter serial data outputs Data is shifted out lsb first on this pin at the falling edge of the serial clock source The output is held high when the transmitter is...

Page 72: ...es data input for the serial communication port to the BDM module I Development Serial Output DSO This internally registered signal provides serial output communication for BDM module responses O Proc...

Page 73: ...ted to VSS to prevent unintentional activation of test functions I PLL Test PLL_TEST Reserved for factory testing only and should be treated as a no connect NC O Table 2 23 Power and Ground Pins Signa...

Page 74: ...nductor 2 4 External Boot Mode After reset the address bus data bus FlexBus control signals and SDRAM control signals default to their bus functionalities All other signals default to GPIO inputs if a...

Page 75: ...ard object file compatibility to the Version 2 V2 ColdFire core It is a step on the ColdFire core roadmap of providing higher performance embedded microprocessors Specific enhancements include a 4 sta...

Page 76: ...stages include the following Four stage instruction fetch pipeline IFP plus optional instruction buffer stage Instruction address generation IAG Calculates the next prefetch address Instruction fetch...

Page 77: ...d loaded into the instruction registers The resulting pipeline and local bus structure allow the V3 ColdFire core to deliver sustained high performance across a variety of demanding embedded applicati...

Page 78: ...registers D0 D7 A0 A7 32 bit program counter PC 8 bit condition code register CCR EMAC registers Four 48 bit accumulator registers partitioned as follows Four 32 bit accumulators ACC0 ACC3 Eight 8 bi...

Page 79: ...Undefined No 4 2 3 4 6 0x807 MAC Accumulator 0 1 Extension Bytes ACCext01 32 R W Undefined No 4 2 4 4 7 0x808 MAC Accumulator 2 3 Extension Bytes ACCext23 32 R W Undefined No 4 2 4 4 7 0x80E Conditio...

Page 80: ...two program visible 32 bit registers does not identify one as the SSP and the other as the USP Instead the hardware uses one 32 bit register as the active A7 and the other as OTHER_A7 Thus the registe...

Page 81: ...ion references to the stack pointer explicit or implicit access the active A7 register NOTE The SSP is loaded during reset exception processing with the contents of location 0x0000_0000 3 2 4 Conditio...

Page 82: ...h prediction bit Alters the static prediction algorithm used by the branch acceleration logic in the IFP on forward conditional branches 0 Predicited as not taken 1 Predicted as taken 6 5 Reserved mus...

Page 83: ...R are accessible The control bits indicate the following states for the processor trace mode T bit supervisor or user mode S bit and master or interrupt state M bit All defined bits in the SR have rea...

Page 84: ...upt exception and software can set it during execution of the RTE or move to SR instructions 11 Reserved must be cleared 10 8 I Interrupt level mask Defines current interrupt level Interrupt requests...

Page 85: ...riginal ColdFire Instruction Set Architecture ISA_A was derived from the M68000 family opcodes based on extensive analysis of embedded application code The ISA was optimized for code compiled IAG IC 1...

Page 86: ...vision ISA_A to form revision ISA_A For more details see the ColdFire Family Programmer s Reference Manual 3 3 3 Exception Processing Overview Exception processing for ColdFire processors is streamlin...

Page 87: ...efined in the vector base register The index into the exception table is calculated as 4 vector number After the exception vector has been fetched the vector contents determine the address of the firs...

Page 88: ...ongword frame format See Table 3 6 6 7 0x018 0x01C Reserved 8 0x020 Fault Privilege violation 9 0x024 Next Trace 10 0x028 Fault Unimplemented line A opcode 11 0x02C Fault Unimplemented line F opcode 1...

Page 89: ...struction for execution Therefore faults during instruction prefetches followed by a change of instruction flow do not generate an exception When the processor attempts to execute an instruction with...

Page 90: ...NOP instruction 3 3 4 2 Address Error Exception Any attempted execution transferring control to an odd instruction address if bit 0 of the target address is set results in an address error exception...

Page 91: ...s a privilege violation exception See ColdFire Programmer s Reference Manual for a list of supervisor mode instructions There is one special case involving the HALT instruction Normally this opcode is...

Page 92: ...n step 2 Because ColdFire processors do not support any hardware stacking of multiple exceptions it is the responsibility of the operating system to check for trace mode after processing other excepti...

Page 93: ...The TRAP n instruction always forces an exception as part of its execution and is useful for implementing system calls The TRAP instruction may be used to change from user to supervisor mode 3 3 4 12...

Page 94: ...he second longword at address 0x0000_0004 is loaded into the program counter After the initial instruction is fetched from memory program execution begins at the address in the PC If an access error o...

Page 95: ...resent in core 1 Divide execute engine is present in core 13 EMAC EMAC present This bit signals if the optional enhanced multiply accumulate EMAC execution engine is present in processor core 0 EMAC e...

Page 96: ...Z Cache line size This field is fixed to a hex value of 0x0 indicating a 16 byte cache line size 29 24 Reserved 23 16 Reserved 15 14 MBSZ Bus size Defines the width of the ColdFire master bus datapath...

Page 97: ...es not experience any sequence related pipeline stalls The most common example of stall involves consecutive store operations excluding the MOVEM instruction For all STORE operations except MOVEM cert...

Page 98: ...s to both forms of absolute addressing xxx w and xxx l Table 3 11 Misaligned Operand References address 1 0 Size Bus Operations Additional C R W 01 or 11 Word Byte Byte 2 1 0 if read 1 0 1 if write 01...

Page 99: ...6 Ay 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 Ay Xi SF 4 1 0 4 1 1 4 1 1 4 1 1 xxx w 3 1 0 3 1 1 3 1 1 3 1 1 xxx l 3 1 0 3 1 1 3 1 1 3 1 1 d16 PC 3 1 0 3 1 1 3 1 1 3 1 1 3 1 1 d8 PC Xi SF 4 1 0 4 1 1 4 1 1 4...

Page 100: ...L imm Dx 1 0 0 ADDQ L imm ea 1 0 0 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 ADDX L Dy Dx 1 0 0 AND L ea Rx 1 0 0 3 1 0 3 1 0 3 1 0 3 1 0 4 1 0 3 1 0 1 0 0 AND L Dy ea 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 A...

Page 101: ...1 0 3 1 0 1 0 0 OR L Dy ea 3 1 1 3 1 1 3 1 1 3 1 1 4 1 1 3 1 1 ORI L imm Dx 1 0 0 REMS L ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 REMU L ea Dx 35 0 0 38 1 0 38 1 0 38 1 0 38 1 0 SUB L ea Rx 1 0 0 3 1...

Page 102: ...tion time is 1 0 0 3 The execution time for STOP is the time required until the processor begins sampling continuously for interrupts 4 PEA execution times are the same for d16 PC 5PEA execution times...

Page 103: ...E L Raccx ea x 1 0 0 2 MOVE L MACSR ea x 1 0 0 MOVE L Rmask ea x 1 0 0 MOVE L Raccext01 ea x 1 0 0 MOVE L Raccext23 ea x 1 0 0 MSAC L Ry Rx Raccx 1 0 0 MSAC W Ry Rx Raccx 1 0 0 MSAC L Ry Rx ea Rw Racc...

Page 104: ...FP and OEP the resulting execution times can vary from 1 to 3 cycles For the remaining ea values for the JSR instruction the branch acceleration logic is not used and the execution times are fixed 3 F...

Page 105: ...he execution times in the BRA Bcc Table 3 19 assume that CCR P is cleared Another representation of the Bcc execution times is shown in Table 3 20 The execution time for the predicted correctly as tak...

Page 106: ...ColdFire Core 3 32 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 107: ...lator The EMAC features a four stage pipeline optimized for 32 bit operands with a fully pipelined 32 32 multiply array and four 48 bit accumulators The first ColdFire MAC supported signed and unsigne...

Page 108: ...le cycle pipelined operations with a possible accumulation after product generation This functionality is common in many signal processing applications The ColdFire core architecture is also modified...

Page 109: ...32 R W Undefined 4 2 3 4 6 0x80A MAC Accumulator 2 ACC2 32 R W Undefined 4 2 3 4 6 0x80B MAC Accumulator 3 ACC3 32 R W Undefined 4 2 3 4 6 1 The values listed in this column represent the Rc field us...

Page 110: ...F I Fractional integer mode Determines whether input operands are treated as fractions or integers 0 Integers can be represented in signed or unsigned notation depending on the value of S U 1 Fraction...

Page 111: ...Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the result cannot be represented in the limited width of the EMAC V is set only if a product overflow occurs or the ac...

Page 112: ...An value calculation is also shown Use of the post increment addressing mode An with the MASK is suggested for circular queue implementations Figure 4 3 Mask Register MASK 4 2 3 Accumulator Registers...

Page 113: ...BDM read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R Accumulator W Reset Table 4 5 ACC0 3 Field Descriptions Field Description 31 0 Accumulator Store...

Page 114: ...s Signed integers Unsigned integers Signed fixed point fractional numbers The EMAC is optimized for single cycle pipelined 32 32 multiplications For word and longword sized integer input operands the...

Page 115: ...n contents the specific definitions are if MACSR 6 5 00 signed integer mode Complete Accumulator 47 0 ACCextn 15 0 ACCn 31 0 if MACSR 6 5 01 or 11 signed fractional mode Complete Accumulator 47 0 ACCe...

Page 116: ...e large data blocks by generating line sized burst references The ability to load an operand simultaneously from memory into a register and execute a MAC instruction makes some DSP operations such as...

Page 117: ...quires that special care during the EMAC s save restore process In particular any result rounding modes must be disabled during the save restore process so the exact bit wise contents of the EMAC regi...

Page 118: ...ultiply Unsigned mulu ea y Dx Multiplies two unsigned operands yielding an unsigned result Multiply Accumulate mac Ry RxSF ACCx msac Ry RxSF ACCx Multiplies two operands and adds subtracts the product...

Page 119: ...s EMAC timing Figure 4 9 EMAC Specific OEP Sequence Stall In Figure 4 9 the OEP stalls the store accumulator instruction for three cycles the EMAC pipleline depth minus 1 The minus 1 factor is needed...

Page 120: ...can be represented is 1 whose internal representation is 0x8000 and 0x8000_0000 respectively The largest positive word is 0x7FFF or 1 2 15 the most positive longword is 0x7FFF_FFFF or 1 2 31 4 3 5 MAC...

Page 121: ...C instruction functionality This example is presented as a case statement covering the three basic operating modes with signed integers unsigned integers and signed fractionals Throughout this example...

Page 122: ...47 0 product 47 0 check for accumulation overflow if accumulationOverflow 1 then MACSR PAVn 1 MACSR V 1 if MACSR OMC 1 then accumulation overflow saturationMode enabled if result 47 1 then result 47 0...

Page 123: ...ro fill else product 71 64 8 product 63 sign extend if inst MSAC then result 47 0 ACCx 47 0 product 71 24 else result 47 0 ACCx 47 0 product 71 24 check for accumulation overflow if accumulationOverfl...

Page 124: ...ero fill to 48 bits before performing any scaling product 47 40 0 zero fill upper byte scale product before combining with accumulator switch SF 2 bit scale factor case 0 no scaling specified break ca...

Page 125: ...ult 47 0 0xffff_ffff_ffff transfer the result to the accumulator ACCx 47 0 result 47 0 MACSR V MACSR PAVn MACSR N ACCx 47 if ACCx 47 0 0x0000_0000_0000 then MACSR Z 1 else MACSR Z 0 if ACCx 47 32 0x00...

Page 126: ...Enhanced Multiply Accumulate Unit EMAC 4 20 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 127: ...egration of the cache Figure 5 1 Unified Cache Organization The cache supports operation of copyback write through or cache inhibited modes A nonblocking cache services read hits or write hits from th...

Page 128: ...the Rc field used when accessing the core registers via the BDM port For more information see Chapter 36 Debug Module Register Width bits Access Reset Value Written with MOVEC Section Page 0x002 Cache...

Page 129: ...explicitly This bit is always read as a 0 Caches are not cleared on power up or normal reset as shown in Figure 5 5 0 No invalidation is performed 1 Initiate invalidation of the entire cache The cache...

Page 130: ...r 1 Enable the processor s use of the User Stack Pointer 3 0 Reserved should be cleared BDM 0x004 ACR0 0x005 ACR1 Access MOVEC write only Debug read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 131: ...e Specifies whether only user or supervisor accesses are allowed in this address range or if the type of access is a don t care 00 Match addresses only in user mode 01 Match addresses only in supervis...

Page 132: ...should be cleared explicitly by setting CACR CINVA before the cache is enabled B After the entire cache is flushed cacheable entries are loaded first in way 0 If way 0 is occupied the cacheable entry...

Page 133: ...y 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Invalid V 0 Valid not modified V 1 M 0 Valid modified V 1 M 1 At reset cache contents are indeterminate V...

Page 134: ...de the data in memory out of date If the memory location is write through the write is passed on to system memory and the M bit is never used The tag does not have TT or TM bits To allocate a cache en...

Page 135: ...o memory occurs The following exceptions apply Read hits cannot change the status bits and no deallocation or replacement occurs the data or instructions are read from the cache If the cache hits on a...

Page 136: ...1 Cacheable Accesses If ACRn CM or the default field of the CACR indicates write through or copyback the access is cacheable A read access to a write through or copyback region is read from the cache...

Page 137: ...e is stored in the fill buffer and remains valid there the cache can service additional read accesses from this buffer until another fill occurs or a cache invalidate all operation occurs If ACRn CM i...

Page 138: ...ut loading the corresponding cache line into the cache 5 3 5 3 Read Hit On a read hit the cache provides the data to the processor core and the cache line state remains unchanged If the cache mode cha...

Page 139: ...including requests for reading new cache lines and writing modified cache lines to memory The following sections describe memory accesses resulting from cache fill and push operations 5 3 7 1 Cache F...

Page 140: ...ruction is held in the pipeline until external bus transfer termination is received Therefore each write is stalled for 5 cycles making the minimum write time equal to 6 cycles when the store buffer i...

Page 141: ...ing the cache and for identifying cache lines to be deallocated is otherwise unchanged If ways 2 and 3 are entirely invalid cacheable accesses are first allocated in way 2 Way 3 is not used until the...

Page 142: ...cacheable access Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Way 0 Way 1 Way 2 Way 3 Invalid V 0 Valid not modified V 1 M 0 Valid modified V 1 M 1 After reset the cache is invalidated then ways 0...

Page 143: ...ache way 5 3 10 Cache Operation Summary This section gives operational details for the cache and presents cache line state diagrams Using the V and M bits the cache supports a line based protocol allo...

Page 144: ...e C W V1 Read new line from memory and update cache supply data to processor stay in valid state CD1 Push modified line to buffer read new line from memory and update cache supply data to processor wr...

Page 145: ...go to modified state CD4 Write data to cache stay in modified state Write hit write through WI4 Not possible WV4 Write data to memory and to cache stay in valid state WD4 Write data to memory and to c...

Page 146: ...Write hit write through WI4 Not possible Cache invalidate C W I5 No action Stay in invalid state Cache push C W I6 No action Stay in invalid state Cache push C W I7 No action Stay in invalid state Tab...

Page 147: ...Write miss write through WD3 Write data to memory stay in modified state Cache mode changed for the region corresponding to this line To avoid this state execute a CPUSHL instruction or set CACR CINV...

Page 148: ...Cache 5 22 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 149: ...ory referencing commands from the debug module Depending on configuration information processor references may be sent to the cache and the SRAM block simultaneously If the reference maps into the reg...

Page 150: ...e 0x8000_0000 0x8FFF_8000 The adress must be 0 modulo 32 K Set the RAMBAR register appropriately By default the RAMBAR is invalid but the backdoor is enabled In this state any core accesses to the SRA...

Page 151: ...r has priority Priority is determined according to the following table Note The recommended setting maximum performance for the priority bits is 00 9 BDE Backdoor Enable Allows access by non core bus...

Page 152: ...to initialize the SRAM The code sets the base address of the SRAM at 0x8000_0000 and initializes the SRAM to zeros RAMBASE EQU 0x80000000 set this variable to 0x80000000 RAMVALID EQU 0x00000001 5 1 C...

Page 153: ...Power Management As noted previously depending on the RAMBAR defined configuration instruction fetch and operand read accesses may be sent to the SRAM and cache simultaneously If the access maps to t...

Page 154: ...Static RAM SRAM 6 6 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 155: ...ck the device directly The clock module contains Crystal amplifier and oscillator OSC Dithering phase locked loop PLL Status and control registers Control logic NOTE Throughout this manual fsys refers...

Page 156: ...0 eDMA SDRAMC FlexBus FEC Watchdog Timer PIT DMA Timers QSPI UART I2 C Clock Module GPIO BDM is asserted D6 when RCON is asserted and MISCCR LIMP FlexCAN SSI RNG SKHA MDHA LCD PWM Oscillator EXTAL32K...

Page 157: ...set 32 32 768 kHz reference crystal oscillator for the real time clock RTC module Input clock used is programmable within the RTC 7 1 3 Modes of Operation The PLL operational mode must be configured d...

Page 158: ...gh the use of RCON the device may be booted into a low frequency limp mode in which the PLL is bypassed and the device runs from a factor of the input clock EXTAL In this mode EXTAL feeds a 5 bit prog...

Page 159: ...ignal can support systems using FB_CLK as the clock source See Section 8 2 5 Low Power Control Register LPCR for more information about operating the PLL in stop mode There is also a fast wakeup optio...

Page 160: ...ss 0xFC0C_0000 PODR Access User read write 7 6 5 4 3 2 1 0 R CPUDIV BUSDIV W Reset 0 0 1 0 0 1 1 0 Figure 7 3 PLL Output Divider Register PODR Table 7 3 PODR Field Descriptions Field Description 7 4 C...

Page 161: ...percentages observed are slightly larger than these targets See Section 7 3 2 Dithering Waveform Definition for more information Deviation 0 75 DITHDEV 0 75 Note This field should only be written whe...

Page 162: ...esults in unpredictable PLL operation Note This field should only be written when dithering mode is disabled PCR DITHEN 0 Else unpredictable PLL operation results Address 0xFC0C_000C PFDR Access User...

Page 163: ...non dithered operation by clearing the PCR DITHEN bit After this occurs the PLL synchronizes the new value with the VCO clock domain Then the transition from dithered operation to non dithered operat...

Page 164: ...simulation The actual percentages achieved may be numerically different than the percentages listed in the specification however the actual percentages achieved are in proportion to each other and are...

Page 165: ...n each mode 7 3 5 Clock Operation During Reset This section describes the reset operation of the PLL Power on reset and normal reset are described 7 3 5 1 Power On Reset POR After VDDPLL and the input...

Page 166: ...ck until RESET is negated The MISCCR PLLLOCK bit is cleared and remains cleared while the PLL is acquiring lock This bit is set after the PLL lock period of 1 ms has passed CAUTION When running in an...

Page 167: ...Register Width bits Access Reset Value Section Page Supervisor Access Only Registers1 0xFC04_0013 Wakeup Control Register WCR 8 R W 0x00 8 2 1 8 2 0xFC04_002C Peripheral Power Management Set Register...

Page 168: ...se related to the high speed processor core are disabled 4 After entering the low power mode the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests...

Page 169: ...led 1 Low power mode entry is enabled 6 3 Reserved should be cleared 2 0 PRILVL Exit low power mode interrupt priority level This field defines the interrupt priority level needed to exit the low powe...

Page 170: ...emory map The PPMR registers provide a unique control bit for each of these address spaces that defines whether the module clock for the given space is enabled or disabled 6 SAMCD Set all module clock...

Page 171: ...4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 CD34 CD33 CD32 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 8 4 Peripheral Power Management High Register PPMHR1 Table 8 5 PPMHR1 CDn Assignments Slot Number CD...

Page 172: ...D31 CD30 CD29 CD28 0 CD26 CD25 CD24 CD23 CD22 CD21 0 CD19 CD18 CD17 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 CD12 0 0 0 CD8 0 0 0 0 0 CD2 0 0 W Reset 0 0...

Page 173: ...and module operation during low power modes 24 CD24 UART0 25 CD25 UART1 26 CD26 UART2 28 CD28 DMA Timer 0 29 CD29 DMA Timer 1 30 CD30 DMA Timer 2 31 CD31 DMA Timer 3 Table 8 8 PPMHR PPMLR Field Descr...

Page 174: ...ice stops executing code upon issue of a STOP instruction However no clocks are disabled 5 FWKUP Fast wake up Determines whether the system clocks are enabled upon wake up from stop mode This bit must...

Page 175: ...d to exit a low power mode and return to run mode Wake up events consist of any of these conditions Any type of reset Any valid enabled interrupt request Exiting from low power mode via an interrupt r...

Page 176: ...during any low power mode No recovery time is required when exiting any low power mode 8 3 4 2 Internal SRAM The SRAM is disabled during any low power mode No recovery time is required when exiting a...

Page 177: ...ins enabled during wait or doze modes then a watchdog timer timeout may generate a reset to exit these low power modes When the CPU is inactive a software reset cannot be generated to exit any low pow...

Page 178: ...s capable of bringing the device out of a low power mode by generating an interrupt upon completion of a transfer or an error condition The completion of transfer interrupt is generated when DMA inter...

Page 179: ...N waits for all internal activity other than in the CAN bus interface to complete and then the following occurs The FlexCAN shuts down its clocks stopping most of the internal circuits to achieve maxi...

Page 180: ...ogrammable Interrupt Timers PIT0 3 In stop mode or in doze mode if so programmed in the PCSRn register the programmable interrupt timer PIT ceases operation and freezes at the current value When exiti...

Page 181: ...byte transfer or the reception of a calling address matching its own specified address when in slave receive mode In stop mode the I2 C module stops immediately and freezes operation register values a...

Page 182: ...ontroller Enabled N A Enabled N A Stopped N A Fast Ethernet Controller Enabled Interrupt Enabled Interrupt Stopped N A USB Host Enabled Interrupt Enabled Interrupt Stopped N A USB OTG Enabled Interrup...

Page 183: ...dependent on programmable bits in the peripheral register map 2 The BDM logic is clocked by a separate TCLK clock Entering halt mode via the BDM port exits any lower power mode Upon exit from halt mo...

Page 184: ...Power Management 8 18 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 185: ...ference Selects output pad drive strength Selects boot device and data port size Selects bus monitor configuration Selects low power configuration 9 1 3 Modes of Operation The only chip operating mode...

Page 186: ...set determine the chip mode of operation boot device clock mode and certain module configurations after reset NOTE It is recommended that the logic levels for reset configuration on D 9 86 1 be active...

Page 187: ...0 See Note 1 Note Reset value depends upon chosen reset configuration Default reset value RCON is not asserted is 0x0001 Figure 9 2 Chip Configuration Register CCR Table 9 3 CCR Field Descriptions Fie...

Page 188: ...set Address 0xFC0A_0008 RCON Access Supervisor read only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 CSC 0 LIMP LOAD BOOTPS OSC MODE PLL MODE 1 W Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Figure 9...

Page 189: ...cks 1 Limp mode low power clock divider drives system clocks Note The transient behavior of the system when writing this bit cannot be predicted When any USB wake up event is detected this bit is clea...

Page 190: ...clock source to the USB modules 0 60 MHz USB clock obtained though divide by 3 CPU operating at 180 MHz 1 60 MHz USB clock obtained though divide by 4 CPU operating at 240 MHz 0 USBSRC USB clock sourc...

Page 191: ...on could result Address 0xFC0A_0014 UHCSR Access Supervisor read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R PORTIND 0 0 0 0 0 0 0 0 0 0 0 WKUP UHMIE XPDE W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Fig...

Page 192: ...bled When set it asserts an interrupt if the UOMIE bit is set 8 DPPU D pull up control Indicates pull up on D for FS only applications is enabled When set it asserts an interrupt if the UOMIE bit is s...

Page 193: ...ated from any of the following bits of the UOCSR DPPD DMPD DRV_VBUS CRG_VBUS DCR_VBUS DPPU and WKUP 0 Interrupt sources are disabled 1 Interrupt sources are enabled 0 XPDE On chip transceiver pull dow...

Page 194: ...t1 1 Modifying the default configurations is possible only if the external RCON pin is asserted Pin s Affected Default Configuration Override Pins in Reset2 Function None RCON 1 0 D1 PLL Mode 0 180 60...

Page 195: ...B_CS0 is asserted for the initial boot fetch accessed from address 0x0000_0000 for the stack pointer and address 0x0000_0004 for the program counter PC It is assumed that the reset vector loaded from...

Page 196: ...select configuration FB_CS 5 4 is selected during reset and reflected in the CCR CSC field After reset is exited the chip select configuration cannot be changed Table 9 10 shows the different chip sel...

Page 197: ...1 Reset Controller Block Diagram 10 1 2 Features Module features include the following Six sources of reset External Power on reset POR Core watchdog timer On chip watchdog timer Phase locked loop PLL...

Page 198: ...options 10 3 Memory Map Register Definition The reset controller programming model consists of these registers Reset control register RCR which selects reset controller functions Reset status register...

Page 199: ...Field Descriptions Field Description 7 SOFTRST Allows software to request a reset The reset caused by setting this bit clears this bit 1 Software reset request 0 No software reset request 6 FRCRSTOUT...

Page 200: ...r timeout 1 Last reset caused by watchdog timer timeout 3 POR Power on reset flag Indicates that the last reset was caused by a power on reset 0 Last reset not caused by power on reset 1 Last reset ca...

Page 201: ...y 512 cycles Then the device exits reset and begins operation 10 4 1 4 Core Watchdog Timer Reset A core watchdog timer timeout causes timer reset request to be recognized and latched If the RESET pin...

Page 202: ...s out or if software requests a reset the reset control logic latches the reset request internally At this point the RSTOUT pin is asserted 5 The reset control logic waits until the RESET signal is ne...

Page 203: ...initiated by power on reset 1 the same reset sequence is followed as for the other asynchronous reset sources 10 4 3 Concurrent Resets This section describes the concurrent resets As in the previous...

Page 204: ...Reset Controller Module 10 8 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 205: ...servicing action does not occur the CWT times out with a programmed response system reset or interrupt to allow recovery or corrective action to be taken NOTE The core watchdog timer is available to...

Page 206: ...C 32 R W 0x4444_4444 11 2 3 11 4 0xFC00_002C Peripheral Access Control Register D PACRD 32 R W 0x4444_4444 11 2 3 11 4 0xFC00_0040 Peripheral Access Control Register E PACRE 32 R W 0x4444_4444 11 2 3...

Page 207: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 R MPROT0 MPROT1 MPROT2 0 1 1 1 MPROT4 MPROT5 MPROT6 0 1 1 1 W Reset 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 Figure 11 1 Master Privilege Registe...

Page 208: ...he privilege level of the master is determined 0 Accesses from this master are forced to user mode 1 Accesses from this master are not forced to user mode Address 0xEC00_0000 MPR1 Access User read wri...

Page 209: ...38 0 1 0 0 W Reset 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 Figure 11 8 Peripheral Access Control Register E PACRE Address 0xFC00_0044 PACRF Access User read write 31 30 29 28 2...

Page 210: ...Interrupt Controller IACK 22 PACR22 I2 C 23 PACR23 QSPI 24 PACR24 UART0 25 PACR25 UART1 26 PACR26 UART2 28 PACR28 DMA Timer 0 29 PACR29 DMA Timer 1 30 PACR30 DMA Timer 2 31 PACR31 DMA Timer 3 32 PACR...

Page 211: ...Description 3 Reserved should be cleared 2 SP Supervisor protect Determines whether the peripheral requires supervisor privilege level for access 0 This peripheral does not require supervisor privile...

Page 212: ...eserved should be cleared 3 BME Bus monitor timeout enable 0 BMT disabled 1 BMT enabled 2 0 BMT Bus monitor timeout period Indicates the timeout period in internal bus cycles for the bus monitor 000 1...

Page 213: ...e CWT generates an interrupt to the core Refer to Chapter 14 Interrupt Controller Modules for details on setting its priority level 01 The first time out generates an interrupt to the processor and if...

Page 214: ...BW bits Address 0xFC04_001F SCMISR Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 CFEI CWIC W w1c w1c Reset 0 0 0 0 0 0 0 0 Figure 11 16 SCM Interrupt Status Register SCMISR Table 11 8 SCMISR Fi...

Page 215: ...nd GBW are cleared then SBE is ignored 8 GBW Global burst enable for writes Allows bursts to happen on write transactions to the crossbar switch slaves from the LCD controller USB host and USB On the...

Page 216: ...cess User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 ECFEI W Reset 0 0 0 0 0 0 0 0 Figure 11 19 Core Fault Interrupt Enable Register CFIER Table 11 11 CFIER Field Descriptions Field Description 7 1 Re...

Page 217: ...direction of the last faulted core access 0 Core read access 1 Core write access 6 4 SIZE Indicates the size of the last faulted core access 000 8 bit core access 001 16 bit core access 010 32 bit co...

Page 218: ...t or if a bus transaction becomes hung The core watchdog timer can be enabled through CWCR CWE it is disabled at reset If enabled the CWT requires the periodic execution of a core watchdog servicing s...

Page 219: ...et a system reset is required to clear it For certain values in the CWCR CWRI field the CWT generates an interrupt response to a time out For these configurations the SCMISR register provides a progra...

Page 220: ...System Control Module SCM 11 16 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 221: ...rs and four slaves 7Mx4S connected to the crossbar switch The seven masters are the ColdFire core eDMA controller FEC LCD controller USB host USB OTG modules and a reserved master for factory test The...

Page 222: ...fies cacheable addresses e g ADDR 31 equals 0 identifies the cacheable space Table 12 1 Crossbar Switch Master Slave Assignments Master Modules Crossbar Port Module Master 0 M0 ColdFire core Master 1...

Page 223: ...around manner to give all masters fair access to the slave See Section 12 5 1 2 Round Robin Priority Operation 12 4 Memory Map Register Definition Two registers reside in each slave port of the crossb...

Page 224: ...5 Address 0xFC00_4100 XBS_PRS1 0xFC00_4400 XBS_PRS4 0xFC00_4600 XBS_PRS6 0xFC00_4700 XBS_PRS7 Access Supervisor read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 225: ...n 19 Reserved must be cleared 18 16 M4 Master 4 LCD Controller priority See M7 description 15 11 Reserved must be cleared 10 8 M2 Master 2 FEC priority See M7 description 7 Reserved must be cleared 6...

Page 226: ...the arbitration policy for the slave port 0 Fixed priority 1 Round robin rotating priority 7 6 Reserved must be cleared 5 4 PCTL Parking control Determines the slave port s parking control The low po...

Page 227: ...r port number of the current bus master for this slave Master port numbers are compared modulo the total number of bus masters i e take the requesting master port number minus the current bus master s...

Page 228: ...Crossbar Switch XBS 12 8 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 229: ...ary function many of the pins may be used as general purpose digital I O GPIO pins In some cases the pin function is set by the operating mode and the alternate pin functions are not supported Each GP...

Page 230: ...C_SCL PQSPI2 QSPI_DIN U2CTS PQSPI1 QSPI_DOUT I2C_SDA PQSPI0 Port Port FECH Port FEC_TXD0 ULPI_DATA0 PFECH5 FEC_COL ULPI_CLK PFECH4 FEC_RXCLK ULPI_NXT PFECH3 FEC_RXDV ULPI_STP PFECH2 FEC_TXCLK PFECH7 F...

Page 231: ...and CS are configured for external memory They are available for the user as GPIO if the corresponding registers are set appropriately All other ports default to GPIO after reset NOTE In this table a...

Page 232: ...C16 D15 A10 O SDVDD D13 D16 D16 A 9 0 SD_A 9 0 3 O SDVDD D14 E11 14 F11 F14 G14 E14 E16 F13 F16 G16 G14 E14 E16 F13 F16 G16 G14 D 31 16 SD_D 31 16 4 I O SDVDD H3 H1 J4 J1 K1 L4 M2 M3 N1 N2 P1 P2 N3 M1...

Page 233: ...SD_CS0 O SDVDD E2 H1 H1 SD_DQS3 O SDVDD H5 L1 L1 SD_DQS2 O SDVDD K6 T6 T6 SD_SCAS O SDVDD L3 P3 P3 SD_SRAS O SDVDD M1 R3 R3 SD_SDR_DQS O SDVDD K4 P1 P1 SD_WE O SDVDD D1 H3 H3 External Interrupts Port...

Page 234: ...EC_RXD 3 1 PFECL 3 1 ULPI_DATA 7 5 I EVDD E7 A6 B6 E7 A6 B6 FEC_RXER PFECL0 I EVDD D4 D4 LCD Controller LCD_D17 PLCDDH1 CANTX O EVDD C9 LCD_D16 PLCDDH0 CANRX O EVDD D9 LCD_D17 PLCDDH1 O EVDD A6 C9 LCD...

Page 235: ...I O USB VDD H13 L16 L16 USBHOST_M I O USB VDD K13 M15 M15 USBHOST_P I O USB VDD J12 M16 M16 FlexCAN MCF53281 MCF5329 only CANRX and CANTX do not have dedicated bond pads Please refer to the following...

Page 236: ..._CS1 PQSPI4 PWM7 USBOTG_ PU_EN O EVDD L11 T13 T13 QSPI_CS0 PQSPI3 PWM5 O EVDD P11 P11 QSPI_CLK PQSPI2 I2C_SCL2 O EVDD N10 R12 R12 QSPI_DIN PQSPI1 U2CTS I EVDD L10 N12 N12 QSPI_DOUT PQSPI0 I2C_SDA O EV...

Page 237: ...P10 PST 3 0 O EVDD N8 P8 L9 M9 R10 T10 R11 T11 R10 T10 R11 T11 Test TEST7 I EVDD E10 A16 A16 PLL_TEST8 I EVDD N13 N13 Power Supplies EVDD E6 E7 F5 F7 H9 J8 J9 K8 K9 K11 E8 F5 F8 G5 G6 H5 H6 J11 K11 K...

Page 238: ...dynamically switched by the processor when accessing SDRAM memory space and are included here for completeness 4 Primary functionality selected by asserting the DRAMSEL signal SDR mode Alternate func...

Page 239: ...I_TXD O SSI_TXD U1TXD Table 13 3 GPIO Module Memory Map Address Register Width bits Access Reset Value Section Page Port Output Data Registers 0xFC0A_4000 PODR_FECH 8 R W 0xFF 13 3 1 13 14 0xFC0A_4001...

Page 240: ...8 R W 0x00 13 3 2 13 17 0xFC0A_401E PDDR_QSPI 8 R W 0x00 13 3 2 13 17 0xFC0A_401F PDDR_TIMER 8 R W 0x00 13 3 2 13 17 0xFC0A_4021 PDDR_LCDDATAH 8 R W 0x00 13 3 2 13 17 0xFC0A_4022 PDDR_LCDDATAM 8 R W 0...

Page 241: ...3 4 13 21 0xFC0A_4041 PCLRR_CS 8 W 0x00 13 3 4 13 21 0xFC0A_4042 PCLRR_PWM 8 W 0x00 13 3 4 13 21 0xFC0A_4043 PCLRR_FECI2C 8 W 0x00 13 3 4 13 21 0xFC0A_4045 PCLRR_UART 8 W 0x00 13 3 4 13 21 0xFC0A_4046...

Page 242: ...8 0xFC0A_405A PAR_QSPI 8 R W 0x0000 13 3 5 5 13 26 0xFC0A_405C PAR_TIMER 8 R W 0x00 13 3 5 6 13 27 0xFC0A_405D PAR_LCDDATA 8 R W 0x00 13 3 5 12 13 32 0xFC0A_405E PAR_LCDCTL 16 R W 0x0000 13 3 5 13 13...

Page 243: ...RT 0xFC0A_400E PODR_LCDDATAM 0xFC0A_400F PODR_LCDDATAL 0xFC0A_4011 PODR_LCDCTLL Access User read write 7 6 5 4 3 2 1 0 R PODR_x W Reset 1 1 1 1 1 1 1 1 Figure 13 3 Port x Output Data Registers PODR_x...

Page 244: ...ss User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 PODR_LCDDATAH W Reset 0 0 0 0 0 0 1 1 Figure 13 8 Port LCDDATAH Output Data Register PODR_LCDDATAH Address 0xFC0A_4010 PODR_LCDCTLH Access User read wr...

Page 245: ...onfigures the corresponding pin as an input Address 0xFC0A_4017 PDDR_BUSCTL 0xFC0A_4018 PDDR_BE 0xFC0A_401B PDDR_FECI2C 0xFC0A_401F PDDR_TIMER Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 PDDR_x W...

Page 246: ...R_CS Address 0xFC0A_4016 PDDR_SSI Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 PDDR_SSI W Reset 0 0 0 0 0 0 0 0 Figure 13 15 Port SSI Data Direction Register PDDR_SSI Address 0xFC0A_4021 PDDR_LCDDAT...

Page 247: ...register Writing 0s has no effect Table 13 5 PDDR_x Field Descriptions Field Description PDDR_x Port x output data direction bits 1 Port x pin configured as output 0 Port x pin configured as input No...

Page 248: ...PPDSDR_QSPI Address 0xFC0A_402D PPDSDR_CS Access User read write 7 6 5 4 3 2 1 0 R 0 0 PPDSDR_CS 0 W Reset 0 0 PCS3 PCS4 PCS3 PCS2 PCS1 0 Figure 13 22 Port CS Pin Data Set Data Register PPDSDR_CS Add...

Page 249: ...0 R 0 0 0 0 0 0 0 PPDSDR_ LCDCTLH0 W Reset 0 0 0 0 0 0 0 PLCD CTLH0 Figure 13 25 Port LCDCTLH Pin Data Set Data Register PPDSDR_LCDCTLH Table 13 6 PPDSDR_x Field Descriptions Field Description PPDR_x...

Page 250: ...0xFC0A_4042 PCLRR_PWM Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W PCLRR_PWM Reset 0 0 0 0 0 0 0 0 Figure 13 28 Port PWM Clear Output Data Register PCLRR_PWM Address 0xFC0A_4046 PCLRR_Q...

Page 251: ...SI Address 0xFC0A_4049 PCLRR_LCDDATAH Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W PCLRR_LCDDATAH Reset 0 0 0 0 0 0 0 0 Figure 13 32 Port LCDDATAH Clear Output Data Register PCLRR_LCDDAT...

Page 252: ...R_BUSCTL Table 13 8 PAR_BUSCTL Field Descriptions Field Description 7 PAR_OE 0 OE pin configured for GPIO 1 OE pin configured for external bus OE function 6 PAR_TA 0 TA pin configured for GPIO 1 TA pi...

Page 253: ...CS5 PAR_CS4 PAR_CS3 PAR_CS2 PAR_CS1 0 W Reset 0 0 1 1 1 1 1 0 Figure 13 36 Chip Select Pin Assignment Register PAR_CS Table 13 10 PAR_CS Field Descriptions Field Description 7 6 Reserved should be cle...

Page 254: ...I2C Table 13 11 PAR_FECI2C Field Descriptions Field Description 7 6 PAR_MDC 5 4 PAR_MDIO 3 2 PAR_SCL 1 0 PAR_SDA FEC I2 C pin assignment These bit fields configure the FEC_MDC FEC_MDIO I2C_SCL and I2C...

Page 255: ...PAR_T0IN W Reset 0 0 0 0 0 0 0 0 Figure 13 39 Timer Pin Assignment PAR_TIMER Table 13 13 PAR_TIMER Field Descriptions Field Description 7 6 PAR_T3IN 5 4 PAR_T2IN 3 2 PAR_T1IN 1 0 PAR_T0IN DMA Timer p...

Page 256: ...5 4 PAR_U1TXD UART1 control pin assignment These bit fields configure the UART1 pins for one of their primary functions or GPIO 3 PAR_U0CTS U0CTS pin assignment 0 U0CTS pin configured for GPIO 1 U0CTS...

Page 257: ...s configure the FEC_CRS FEC_RXD3 FEC_RXD2 FEC_RXD1 FEC_RXER FEC_TXD3 FEC_TXD2 FEC_TXD1 and FEC_TXER pins for one of their primary functions or GPIO Note FEC_COL FEC_RXCLK FEC_RXDV FEC_RXD0 FEC_TXCLK F...

Page 258: ...tion 15 14 Reserved should be cleared 13 12 PAR_IRQ6 11 10 PAR_IRQ5 9 8 PAR_IRQ4 7 6 PAR_IRQ2 5 4 PAR_IRQ1 IRQ pin assignment These bit fields configure the IRQ pins for one of their primary functions...

Page 259: ...gured for GPIO function 1 SSI_MCLK pin configured for SSI_MCLK function 6 0 Reserved should be cleared Address 0xFC0A_4051 PAR_PWM Access User read write 7 6 5 4 3 2 1 0 R 0 0 PAR_PWM7 PAR_PWM5 PAR_PW...

Page 260: ...2 1 0 R PAR_LD17 PAR_LD16 PAR_LD15_8 PAR_LD7_0 W Reset 0 0 0 0 0 0 0 0 Figure 13 45 LCD Data Pin Assignment PAR_LCDDATA Table 13 19 PAR_LCDDATA Field Descriptions Field Description 7 6 PAR_LD17 5 4 P...

Page 261: ...LM VSYNC pin configured for LCD controller FLM VSYNC function 6 PAR_LP_HSYNC LCD_LP HSYNC pin assignment 0 LCD_LP HSYNC pin configured as GPIO 1 LCD_LP HSYNC pin configured for LCD controller LP HSYNC...

Page 262: ...rol the strength of the FlexBus upper data pins 00 Half strength 1 8V low power mobile DDR 01 Open drain 10 Full strength 1 8V low power mobile DDR 11 2 5V DDR1 or 3 3V CMOS with roughly equal rise an...

Page 263: ...lf strength 1 8V Mobile DDR 01 Open drain 10 Full strength 1 8V Mobile DDR 11 2 5V DDR1 or 3 3V CMOS with roughly equal rise and fall delays 1 0 MSCR_ SDRAM SD_A10 SD_CAS SD_CKE SD_CS0 SD_DQS 3 2 SD_R...

Page 264: ...SE W Reset 0 0 0 0 0 0 See Note 1 Note Reset state is 0 when RCON 1 and is value of D 5 when RCON 0 Figure 13 49 Drive Strength Control Registers DSCR_x Table 13 23 DSCR_x Field Descriptions Field Des...

Page 265: ...nd U0RTS pins 00 10pF 01 20pF 10 30pF 11 50pF Address 0xFC0A_4071 DSCR_CLKRST Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 RSTOUT_DSE MSCR_FBCLK W Reset 0 0 0 0 See Note 1 1 1 Note Reset state is...

Page 266: ...uts Reading a PODR_x register returns the current state of the register regardless of the state of the corresponding pins Reading a PPDSDR_x register returns the current state of the corresponding pin...

Page 267: ...n Application Information The initialization for the ports module is done during reset configuration All registers are reset to a predetermined state Refer to Section 13 3 Memory Map Register Definiti...

Page 268: ...General Purpose I O Module 13 40 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 269: ...t architecture of ColdFire is exactly the same as the M68000 family where there is a 3 bit encoded interrupt priority level sent from the interrupt controller to the core providing 7 levels of interru...

Page 270: ...re cores In this approach all IACK cycles are directly managed by the interrupt controller so the requesting peripheral device is not accessed during the IACK As a result the interrupt request must be...

Page 271: ...8 14 10 0xFC04_8040 n n 0 63 Interrupt Control Registers ICR0n 8 R W 0x00 14 2 9 14 11 0xFC04_80E0 Software Interrupt Acknowledge SWIACK0 8 R 0x00 14 2 10 14 15 0xFC04_80E0 4n n 1 7 Level n Interrupt...

Page 272: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 14 1 Interrupt Pending Register High IPRHn Table 14 3 IPRHn Field Descriptions Field Description 31 0 INT Interrupt pending Each bit corresponds to...

Page 273: ...el interrupt mask to the status register before setting the mask in the IMR or the module s interrupt mask register After the mask is set return the interrupt mask in the status register to its previo...

Page 274: ...g IPRHn bit reflects the state of the interrupt signal even if the corresponding IMRHn bit is set 0 The corresponding interrupt source is not masked 1 The corresponding interrupt source is masked Addr...

Page 275: ...onding source Address 0xFC04_8014 INTFRCL0 0xFC04_C014 INTFRCL1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R INTFRCL W Reset 0 0 0 0 0...

Page 276: ...not affect the processor s bus master priority 8 6 Reserved must be cleared 5 EMASK If set the interrupt controller automatically loads the level of an interrupt request into the CLMASK current level...

Page 277: ...quest source and the CLMASK register is loaded with the level number associated with the request After the CLMASK register is updated then all interrupt requests with level numbers equal to or less th...

Page 278: ...r value is saved in the SLMASK register Typically after a level n interrupt request is managed the service routine restores the saved level mask value into the current level mask register to re enable...

Page 279: ...0xFC04_801F SLMASK Access User read write 7 6 5 4 3 2 1 0 R 0 0 0 0 SLMASK W Reset 0 0 0 0 1 1 1 1 Figure 14 11 Saved Level Mask Register SLMASK Table 14 13 SLMASK Field Descriptions Field Descriptio...

Page 280: ...NTR INT05 DMA Channel 5 transfer complete Write EDMA_CINTR CINT 5 14 EDMA_INTR INT06 DMA Channel 6 transfer complete Write EDMA_CINTR CINT 6 15 EDMA_INTR INT07 DMA Channel 7 transfer complete Write ED...

Page 281: ...TXB 1 38 EIR UN Transmit FIFO underrun Write EIR UN 1 39 EIR RL Collision retry limit Write EIR RL 1 40 EIR RXF Receive frame interrupt Write EIR RXF 1 41 EIR RXB Receive buffer interrupt Write EIR RX...

Page 282: ...13 BUF9I Message Buffer 9 Interrupt Write 1 to BUF9I after reading as 1 14 BUF10I Message Buffer 10 Interrupt Write 1 to BUF10I after reading as 1 15 BUF11I Message Buffer 11 Interrupt Write 1 to BUF1...

Page 283: ...e IACK is performed near the end of an interrupt service routine and if there are additional active interrupt sources the current interrupt service routine ISR passes control to the appropriate servic...

Page 284: ...upt controller can be broadly partitioned into three activities Address 0xFC04_80E0 SWIACK0 0xFC04_80E0 4n LnIACK0 n 1 7 0xFC04_C0E0 SWIACK1 0xFC04_C0E0 4n LnIACK1 n 1 7 0xFC05_40E0 GSWIACK 0xFC05_40E...

Page 285: ...appropriate interrupt controller Next the interrupt controller extracts the level being acknowledged from address bits 4 2 and then determines the highest unmasked level for the type of interrupt bein...

Page 286: ...serviced first 14 3 3 Low Power Wake up Operation The system control module SCM contains an 8 bit low power control register LPCR to control the low power stop mode This register must be explicitly pr...

Page 287: ...t requests by clearing the appropriate bits in the IMR and lowering the interrupt mask level in the core s status register SR I to an appropriate level 14 4 1 Interrupt Service Routines This section f...

Page 288: ...rvice routine the SR I field is again raised to the original acknowledged level preparing to perform the context switch At the end of segment E the original value in the saved level mask SLMASK is res...

Page 289: ...T signals may be output from the device See Chapter 2 Signal Descriptions to determine which signals are available Figure 15 1 EPORT Block Diagram NOTE The GPIO module must be configured to enable the...

Page 290: ...t logic because no clocks are available 15 3 Interrupt GPIO Pin Descriptions All EPORT pins default to general purpose input pins at reset The pin value is synchronized to the rising edge of FB_CLK wh...

Page 291: ...a bus error 0xFC09_4000 EPORT Pin Assignment Register EPPAR 16 R W 0x0000 15 4 1 15 3 0xFC09_4002 EPORT Data Direction Register EPDDR 8 R W 0x00 15 4 2 15 4 0xFC09_4003 EPORT Interrupt Enable Register...

Page 292: ...ation as input or output Interrupt requests generated in the EPORT module can be masked by the interrupt controller module EPPAR functionality is independent of the selected pin direction Reset clears...

Page 293: ...set EPORT generates an interrupt request when The corresponding bit in the EPORT flag register EPFR is set or later becomes set The corresponding pin level is low and the pin is configured for level...

Page 294: ...EPPDR Address 0xFC09_4006 EPFR Access User read write 7 6 5 4 3 2 1 0 R EPF7 EPF6 EPF5 EPF4 EPF3 EPF2 EPF1 EPF0 W Reset 0 0 0 0 0 0 0 0 Figure 15 7 EPORT Port Flag Register EPFR Table 15 8 EPFR Field...

Page 295: ...ion address calculations and the actual data movement operations along with local memory containing transfer control descriptors for each channel 16 2 Block Diagram Figure 16 1 is a block diagram of t...

Page 296: ...r loop defined by a major iteration count Channel activation via one of three methods Explicit software initiation Initiation via a channel to channel linking mechanism for continual transfers Periphe...

Page 297: ...after the DACKn assertion and on or before the second cycle following the data phase of the last internal bus write see Figure 16 2 If another service request is needed DREQn may simply remain assert...

Page 298: ...rity Table 16 2 eDMA Controller Memory Map Address Register Width bits Access Reset Value Section Page 0xFC04_4000 eDMA Control Register EDMA_CR 32 R W 0x0000_0000 16 6 1 16 4 0xFC04_4004 eDMA Error S...

Page 299: ...byte count must be a multiple of the source and destination transfer sizes All source reads and destination writes must be configured to the natural boundary of the programmed transfer size respectiv...

Page 300: ...s the channel terminates after the read or write transaction which is already pipelined after errant access has completed If a bus error occurs on the last read prior to beginning the write sequence t...

Page 301: ...ion error 1 The last recorded error was a configuration error detected in the TCDn_DADDR field TCDn_DADDR is inconsistent with TCDn_ATTR DSIZE 4 DOE Destination offset error 0 No destination offset co...

Page 302: ...DMA requests from the peripherals to the channels of the eDMA are shown in Table 16 6 Address 0xFC04_400E EDMA_ERQ Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R ERQ 15 ERQ 14 ERQ 13 E...

Page 303: ...l is asserted to the interrupt controller 16 6 5 eDMA Set Enable Request Register EDMA_SERQ The EDMA_SERQ provides a simple memory mapped mechanism to set a given bit in the EDMA_ERQ to enable the DMA...

Page 304: ...ll zeroes Address 0xFC04_4018 EDMA_SERQ Access User write only 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W SAER SERQ Reset 0 0 0 0 0 0 0 0 Figure 16 7 eDMA Set Enable Request Register EDMA_SERQ Table 16 8 EDM...

Page 305: ...causes the corresponding bit in the EDMA_EEI to be cleared Setting the CAEE bit provides a global clear function forcing the EDMA_EEI contents to be cleared disabling all DMA request inputs Reads of...

Page 306: ...CAEE CEEI Reset 0 0 0 0 0 0 0 0 Figure 16 10 eDMA Clear Enable Error Interrupt Register EDMA_CEEI Table 16 11 EDMA_CEEI Field Descriptions Field Description 7 Reserved must be cleared 6 CAEE Clear al...

Page 307: ...register write causes the START bit in the corresponding transfer control descriptor to be set Setting the SAST bit provides a global set function forcing all START bits to be set Reads of this regist...

Page 308: ...able 16 14 EDMA_SSRT Field Descriptions Field Description 7 Reserved must be cleared 6 SAST Set all START bits activates all channels 0 Set only those TCDn_CSR START bits specified in the SSRT field 1...

Page 309: ...egister are enabled by the contents of the EDMA_EEI and then routed to the interrupt controller During the execution of the interrupt service routine associated with any DMA errors it is software s re...

Page 310: ...ible for preemption If any higher priority channel is requesting service the restored channel is suspended and the higher priority channel is serviced Nested preemption attempting to preempt a preempt...

Page 311: ...ity when fixed priority arbitration is enabled Table 16 19 TCDn Memory Structure eDMA Offset TCDn Register Name Abbreviation Width bits 0xFC04_5000 0x20 n Source Address TCDn_SADDR 32 0xFC04_5004 0x20...

Page 312: ...er of 2 size bytes the queue should start at a 0 modulo size address and the SMOD field should be set to the appropriate value for the queue freezing the desired number of upper address bits The value...

Page 313: ...control field or via preemption After the minor count is exhausted the SADDR and DADDR values are written back into the TCD memory the major iteration count is decremented and restored to the TCD mem...

Page 314: ...annel to channel linking is enabled Note This bit must be equal to the BITER E_LINK bit Otherwise a configuration error is reported 14 13 Reserved must be cleared 12 9 LINKCH Link channel number If ch...

Page 315: ...DLAST_SGA Destination last address adjustment or the memory address for the next transfer control descriptor to be loaded into this channel scatter gather If TCDn_CSR E_SG 0 then Adjustment value adde...

Page 316: ...engine initiates a channel service request at the channel defined by these four bits by setting that channel s TCDn_CSR START bit 0 15 Link to DMA channel 0 15 Note When the software loads the TCD th...

Page 317: ...lag signals the channel is currently in execution It is set when channel service begins and the eDMA clears it as the minor loop completes or if any error condition is detected 5 MAJOR_E_LINK Enable c...

Page 318: ...CDn_ SADDR DADDR CITER back to local memory If the major iteration count is exhausted additional processing are performed including the final address pointer updates reloading the TCDn_CITER field and...

Page 319: ...ta two reads are performed then one 32 bit write Transfer Control Descriptor Memory Memory Controller This logic implements the required dual ported controller managing accesses from the eDMA engine a...

Page 320: ...s are initiated and the fetched data is temporarily stored in the data path block until it is gated onto the internal bus during the destination write This source read destination write processing con...

Page 321: ...s and reloading of the BITER field into the CITER Assertion of an optional interrupt request also occurs at this time as does a possible fetch of a new TCD from memory using the scatter gather address...

Page 322: ...d 3 Enable error interrupts in the EDMA_EEI if so desired 4 Write the 32 byte TCD for each channel that may request service 5 Enable any hardware service requests via the EDMA_ERQ 6 Request channel se...

Page 323: ...ts major loop channel linking and scatter gather operations if enabled Table 16 32 shows how each DMA request initiates one minor loop transfer iteration without CPU intervention DMA arbitration can o...

Page 324: ...33 lists the memory array terms and how the TCD settings interrelate Table 16 32 Example of Multiple Loop Iterations Current Major Loop Iteration Count CITER DMA Request Minor Loop Major Loop 3 DMA Re...

Page 325: ...t priority is selected by arbitration and executed by the eDMA engine The hardware service request handshake signals error interrupts and error reporting is associated with the selected channel 16 8 3...

Page 326: ...ongword wide port located at 0x2000 The address offsets are programmed in increments to match the transfer size one byte for the source and four bytes for the destination The final source and destinat...

Page 327: ...s The only fields that change are the major loop iteration count and the final address offsets The eDMA is programmed for two iterations of the major loop transferring 16 bytes per iteration After the...

Page 328: ...cation 0x2014 second iteration of the minor loop e Read byte from location 0x1018 read byte from location 0x1019 read byte from 0x101A read byte from 0x101B f Write longword to location 0x2018 third i...

Page 329: ...TCDn_CSR ACTIVE bit may be inconclusive because the active status may be missed if the channel execution is short in duration The TCD status bits execute the following sequence for a software activat...

Page 330: ...tstanding requests become undefined Channel priorities are treated as equal constantly rotating when round robin arbitration mode is selected The TCDn_CSR ACTIVE bit for the preempted channel remains...

Page 331: ...nd the TCDn_BITER E_LINK bit must equal or a configuration error is reported The CITER and BITER vector widths must be equal to calculate the major loop half way done interrupt point Table 16 35 summa...

Page 332: ...c channel link or dynamic scatter gather request 1 Set the TCDn_CSR MAJOR_E_LINK bit 2 Read back the TCDn_CSR MAJOR_E_LINK bit 3 Test the TCDn_CSR MAJOR_E_LINK request status a If the bit is set the d...

Page 333: ...the upper two bytes of the FlexBus data bus FB_D 31 16 This chapter only uses FB_D 31 0 or FB_D 31 X to designate the data bus but the actual pins used depend on the DRAMSEL setting Take this into con...

Page 334: ...D 31 0 The FB_A 23 0 and FB_D 31 0 buses carry the address and data respectively The number of byte lanes carrying the data is determined by the port size associated with the matching chip select Beca...

Page 335: ...nable signal FB_OE is sent to the interfacing memory and or peripheral to enable a read transfer FB_OE is only asserted during read accesses when a chip select matches the current address decode Becau...

Page 336: ...isters and bit meanings for configuring chip select operation Table 17 2 shows the chip select register memory map The actual number of chip select registers available depends upon the device and its...

Page 337: ...hip Select Address Registers CSARn Table 17 3 CSARn Field Descriptions Field Description 31 16 BA Base address Defines the base address for memory dedicated to chip select FB_CSn BA is compared to bit...

Page 338: ...0x8_0000 0x8_FFFF Likewise for FB_CS0 to access 32 Mbytes of address space starting at location 0x00_0000 FB_CS1 must begin at the next byte after FB_CS0 for a 16 Mbyte address space Then CSAR0 equal...

Page 339: ...for a burst transfer except for the first termination which is controlled by the wait state count The secondary wait state is used only if the SWSEN bit is set Otherwise the WS value is used for all b...

Page 340: ...acknowledge ends the cycle An external FB_TA supersedes the generation of an internal FB_TA 9 SBM Split bus mode For proper operation of the chip select signals this bit must be set when the SDRAM co...

Page 341: ...of byte enable support for these SRAMs 0 FB_BE BWE is not asserted for reads FB_BE BWE is asserted for data write only 1 FB_BE BWE is asserted for read and write accesses 4 BSTR Burst read enable Spec...

Page 342: ...peration differs from other external chip select outputs after system reset After system reset FB_CS0 is asserted for every external access No other chip select can be used until the valid bit CSMR0 V...

Page 343: ...transfers of a longword transfer for the supported port sizes when not in split bus mode For example an 8 bit memory connects to the single lane FB_D 31 24 FB_BE BWE0 A longword transfer through this...

Page 344: ...ird clock edge FB_TA can be negated after this edge and read data can then be tri stated 4 S3 FB_CSn is negated at the fourth rising clock edge This last clock of the bus cycle uses what would be an i...

Page 345: ...r externally then the S1 state continues to repeat Read Data is driven by the external device before the next rising edge of FB_CLK the rising edge that begins S2 with FB_TA asserted S2 All For intern...

Page 346: ...with the full 32 bit address This may be ignored by standard connected devices using non multiplexed address and data buses However some applications may find this feature beneficial The address and...

Page 347: ...23 0 ADDR 23 0 FB_D 31 X ADDR 31 X FB_CSn FB_OE FB_BE BWEn FB_TA S0 S3 1 Select the appropriate slave device Assert FB_TA external termination 3 1 Negate FB_TA external termination 1 Decode address 1...

Page 348: ...tes the basic byte read transfer to an 8 bit device with no wait states The address is driven on the FB_A bus throughout the bus cycle The external device returns the read data on FB_D 31 24 and may t...

Page 349: ...en on the FB_A 0 bus throughout the bus cycle The external device returns the read data on FB_D 31 16 and may tristate the data line or continue driving the data one clock after FB_TA is sampled asser...

Page 350: ...Word Write Transfer Figure 17 15 depicts a longword read from a 32 bit device Figure 17 15 Longword Read Transfer FB_CLK S0 S1 S2 S3 FB_D 31 16 FB_R W FB_TS FB_TA FB_OE FB_CSn FB_BE BWEn DATA 15 0 FB...

Page 351: ...ite bus cycle to provide additional address setup address hold and time for a device to provide or latch data 17 4 5 4 1 Wait States Wait states can be inserted before each beat of a transfer by progr...

Page 352: ...of no wait states Figure 17 17 Basic Read Bus Cycle No Wait States Figure 17 18 Basic Write Bus Cycle No Wait States FB_CLK FB_R W FB_TS S0 S1 S2 S3 DATA FB_A 23 0 ADDR 23 0 FB_D 31 X ADDR 31 X FB_CS...

Page 353: ...State Figure 17 20 Write Bus Cycle One Wait State 17 4 5 4 2 Address Setup and Hold The timing of the assertion and negation of the chip selects byte selects and output enable can be programmed on a...

Page 354: ...Bus Cycle with Two Clock Address Setup No Wait States Figure 17 22 Write Bus Cycle with Two Clock Address Setup No Wait States FB_CLK FB_R W FB_TS S0 AS S1 S2 S3 DATA FB_A 23 0 ADDR 23 0 FB_D 31 X ADD...

Page 355: ...e 17 24 show read and write bus cycles with two clocks of address hold Figure 17 23 Read Cycle with Two Clock Address Hold No Wait States Figure 17 24 Write Cycle with Two Clock Address Hold No Wait S...

Page 356: ...ns The FlexBus can support 2 1 1 1 burst cycles to maximize system performance Delaying termination of the cycle can add wait states If internal termination is used different wait state counters can b...

Page 357: ...Port 2 1 1 1 No Wait States Figure 17 27 shows a longword write to an 8 bit device with burst enabled The transfer results in a 4 beat burst and the data is driven on NOTE The first beat of any write...

Page 358: ...inhibited transfer between states S0 and S1 Figure 17 28 Longword Read Burst Inhibited from 8 Bit Port No Wait States FB_CLK FB_R W FB_TS S0 S1 S2 S2 S2 S3 DATA DATA DATA DATA WS S2 ADDR 1 ADDR 2 ADDR...

Page 359: ...n the first beat However for subsequent beats the CSCRn WS or CSCRn SWS if CSCRn SWSEN is set determines the number of wait states Figure 17 30 Longword Read Burst from 8 Bit Port 3 2 2 2 One Wait Sta...

Page 360: ...e attached device must be able to account for this or a wait state must be added Figure 17 32 Longword Read Burst from 8 Bit Port 3 1 1 1 Address Setup and Hold FB_CLK FB_R W FB_TS S0 S1 WS S2 WS SWS...

Page 361: ...setup and address hold Figure 17 33 Longword Write Burst to 8 Bit Port 3 1 1 1 Address Setup and Hold FB_CLK FB_R W FB_TS S0 AS S1 S2 S2 S2 S2 S3 AH DATA DATA DATA DATA ADDR 1 ADDR 2 ADDR 3 FB_A 23 0...

Page 362: ...second cycle a word transfers with a byte offset of 0x2 The next two bytes are transferred in this cycle In the third cycle byte 3 transfers The byte offset is now 0x0 the port supplies the final byte...

Page 363: ...he DRAM controller for synchronous operations NOTE Unless otherwise noted in this chapter clock refers to the system clock fsys 3 The external data bus is shared between the FlexBus module and the SDR...

Page 364: ...bus mode column address lines 2 bits of bank address and two pinned out chip selects The maximum row bits plus column bits equals 24 in 32 bit bus mode or 25 in 16 bit bus mode Minimum memory configur...

Page 365: ...uration registers SDRAM bank An internal partition in an SDRAM device For example a 64 Mbit SDRAM component might be configured as four 512K x 32 banks Banks are selected through the SD_BA 1 0 signals...

Page 366: ...als and device input buffers and output drivers Timing Assertion Asynchronous for self refresh exit and for output disable Negation Occurs synchronously with SD_CLK SD_CLK SD_CLK O SD_CLK and SD_CLK a...

Page 367: ...h DQS edge rising and falling for SDR operation valid data follows the rising edges only The address correspondence SD_DQS3 SD_D 31 24 SD_DQS2 SD_D 23 16 Note If a read is attempted from a DDR SDRAM c...

Page 368: ...via the SDCR ADDR_MUX bits NOTE When the SDRAMC is configured to support an external 32 bit data bus It is not possible to connect a smaller device s to only part of the SDRAM s data bus For example i...

Page 369: ...1 x 4 00 CA11 CA9 CA8 13 x 10 x 4 01 CA9 CA8 RA12 14 x 9 x 4 10 CA8 RA13 RA12 64M x 4 bit 12 x 12 x 4 00 CA12 CA11 CA9 CA8 13 x 11 x 4 01 CA11 CA9 CA8 RA12 14 x 10 x 4 10 CA9 CA8 RA13 RA12 512 Mbits 1...

Page 370: ...dress lines The SDRAM controller inserts an extra bit CA10 to control the precharge option Table 18 4 Address Multiplexing for 16 bit Bus Mode SDCR ADDR_MUX Internal Address Bits 27 24 IA 27 IA 26 IA...

Page 371: ...x 10 x 4 10 CA9 RA13 RA12 512 Mbits 32 M x 16 bit 12 x 11 x 4 00 CA11 CA9 RA11 0 BA1 0 CA8 0 13 x 10 x 4 01 CA9 RA12 14 x 9 x 4 10 RA13 RA12 64M x 8bit 12 x 12 x 4 00 CA12 CA11 CA9 13 x 11 x 4 01 CA1...

Page 372: ...icron MT48LC4M32B2 and flash such as Spansion AM29LV160D SDR design requires special timing consideration for the SD_DQS 3 signals For reads from DDR SDRAMs the memory drives the DQS pins so that the...

Page 373: ...A 13 11 9 0 A10 AP BA 1 0 SD_A10 SD_A 23 0 SD_CKE SD_CLK SD_CS0 CS SD_RAS SD_SDR_DQS SDWE CLK CKE RAS SD_CAS CAS WE A 15 14 A 13 11 9 0 3 3V Flash A 21 0 D 31 0 WE OE CE R W OE FB_CS0 SDRAM Control S...

Page 374: ...tical timing for DDR SDRAM a number of considerations should be taken into account during PCB layout Minimize overall trace lengths SDRAM Controller 2 5V DDR SDRAM A 13 11 9 0 A10 AP BA 1 0 D 15 0 SD_...

Page 375: ...essor and memory but closest to the processor The SD_CLK and SD_CLK signals can be terminated with a single termination resistor between the two clock phases A 100 120 resistor produces effective term...

Page 376: ...ing SDRAM initialization See Section 18 6 Initialization Application Information for more information on the initialization sequence Table 18 6 SDRAMC Memory Map Address Register Width bits Access Res...

Page 377: ...ister data 17 Reserved must be cleared 16 CMD Command This bit is write only and always returns a 0 when read 1 Generate an LMR LEMR command 0 Do not generate any command 15 0 Reserved must be cleared...

Page 378: ...e SDRAM data sheet does not define tREFI it can be calculated by tREFI tREF rows 15 14 Reserved must be cleared 13 MEM_PS Memory data port size 0 32 bit data bus 1 16 bit data bus 12 Reserved must be...

Page 379: ...ry controller counts the delay in SD_CLK In DDR mode the memory controller counts the delay in 2 x SD_CLK also referred to as SD_CLK2 SD_CLK memory controller clock is the speed of the SDRAM interface...

Page 380: ...cleared 26 24 SWT2RWP Single write to read write precharge delay Limiting case is write to precharge SDR SWT2RWP tWR DDR SWT2RWP tWR 1 Note Count value is in SD_CLK periods for SDR and DDR mode 23 20...

Page 381: ...to nearest integer Example If tRP 20ns and fSD_CLK 99 MHz Suggested value 20ns 99 MHz 1 0 98 round to 1 Note Count value is in SD_CLK periods for SDR and DDR modes 11 8 REF2ACT Refresh to active delay...

Page 382: ...Table 18 10 SDCFG2 Field Descriptions Field Description 31 28 BRD2RP Burst read to read precharge delay Limiting case is read to read SDR BRD2RP BurstLength 1 DDR BRD2RP BurstLength 2 1 27 24 BWT2RWP...

Page 383: ...controller generates the corresponding SDRAM command Table 18 12 lists SDRAM commands supported by the memory controller Table 18 11 SDCSn Field Descriptions Field Description 31 20 CSBA Chip select...

Page 384: ...ddress falls within the active row of an active bank it is a page hit and the read is issued as soon as possible pending any delays required by previous commands If the address is within an inactive b...

Page 385: ...by the WRITE command to the SDRAM The PALL PRE and ACTV commands if necessary can sometimes be issued in parallel with an on going data movement In SDR mode the memory controller issues the burst ter...

Page 386: ...DMR BA values This step can be performed in the same register write in step 2 4 Set the SDMR CMD bit 5 For DDR step 2 to 4 should be performed twice The first is for the extended mode register and the...

Page 387: ...command A3 BT Burst type 0 Sequential 1 Interleaved This setting should not be used because the SDRAMC does not support interleaved bursts A2 A0 BLEN Burst length Determines the number of column locat...

Page 388: ...the memory controller clock is stopped the refresh interval timer must be reset before the memory is reactivated if periodic refresh is to be resumed The refresh interval timer resets by clearing the...

Page 389: ...4 memory clock period delay of the DQS signals across the full range of silicon process voltage and temperature conditions The RD_CLK is an internal reconstructed clock derived from DQS It is twice th...

Page 390: ...to allow read and write accesses The SDRAM controller supports paging mode to maximize the memory access throughout During operation the SDRAM controller maintains an open page for each SD_CS block A...

Page 391: ...er manages the size translation packing unpacking between internal and external DRAM buses The burst size is the processor standard 16 bytes Four beats of 4 bytes on the internal bus four beats of 4 b...

Page 392: ...SDRAM Controller SDRAMC 18 30 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 393: ...iver interface and transceiver function are required to complete the interface to the media The FEC supports three different standard MAC PHY physical interfaces for connection to an external Ethernet...

Page 394: ...r descriptors Address recognition for receive frames Random number generation for transmit collision backoff timer FIFO FEC DMA MII Receive Transmit Controller I O PAD MDO MDEN MDI MII 7 Wire data FIF...

Page 395: ...put lines of the MII interface The FEC DMA block not to be confused with the device s eDMA controller provides multiple channels allowing transmit data transmit descriptor receive data and receive des...

Page 396: ...19 5 11 Full Duplex Flow Control for more details 19 2 2 Interface Options The following interface options are supported A detailed discussion of the interface configurations is provided in Section 1...

Page 397: ...re interface mode this signal should be connected to VSS FEC_RXCLK X X Provides a timing reference for FEC_RXDV FEC_RXD 3 0 and FEC_RXER FEC_RXDV X X Asserting the FEC_RXDV input indicates that the PH...

Page 398: ...s FEC_TXER has no effect at 10 Mbps or when FEC_TXEN is negated Table 19 2 Module Memory Map Address Function 0xFC03_0000 FC03_01FF Control Status Registers 0xFC03_0200 FC03_02FF MIB Block Counters Ta...

Page 399: ...9 4 13 19 19 0xFC03_00EC Opcode Pause Duration OPD 32 R W See Section 19 4 14 19 19 0xFC03_0118 Descriptor Individual Upper Address Register IAUR 32 R W Undefined 19 4 15 19 20 0xFC03_011C Descriptor...

Page 400: ...E_T_FRAME_OK 0xFC03_0250 Frames transmitted with single collision IEEE_T_1COL 0xFC03_0254 Frames transmitted with multiple collisions IEEE_T_MCOL 0xFC03_0258 Frames transmitted after deferral delay IE...

Page 401: ...T_EXCOL XFIFO_UN IEEE_T_MACERR 0xFC03_029C RMON Rx packets 64 bytes bad CRC RMON_R_FRAG 0xFC03_02A0 RMON Rx packets MAX_FL bytes bad CRC RMON_R_JAB 0xFC03_02A4 Reserved RMON_R_RESVD_0 0xFC03_02A8 RMON...

Page 402: ...completion of the frame currently being transmitted This bit is set by one of three conditions 1 A graceful stop initiated by the setting of the TCR GTS bit is now complete 2 A graceful stop initiate...

Page 403: ...can only occur in half duplex mode 19 UN Transmit FIFO underrun Indicates the transmit FIFO became empty before the complete frame was transmitted A bad CRC is appended to the frame fragment and the r...

Page 404: ...in signifying additional descriptors are placed into the transmit descriptor ring The TDAR register is cleared at reset when ECR ETHER_EN is cleared or when ECR RESET is set Address 0xFC03_0010 Access...

Page 405: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 ETHER _EN RESET W Reset 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 19 6 Ethernet Control Register ECR Table 19 9 ECR Field Descriptions Field De...

Page 406: ...tern causes the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine During this time contents of the MMFR register are altered as the c...

Page 407: ...alling edge of FEC_MDC If the internal bus clock is 25 MHz programming this register to 0x0000_0005 results in an FEC_MDC as stated the equation below Eqn 19 1 A table showing optimum values for MII_S...

Page 408: ...les for MSCR Internal FEC Clock Frequency MSCR MII_SPEED FEC_MDC frequency 25 MHz 0x5 2 50 MHz 33 MHz 0x7 2 36 MHz 40 MHz 0x8 2 50 MHz 50 MHz 0xA 2 50 MHz 66 MHz 0xE 2 36 MHz 80 MHz 0x10 2 50 MHz Addr...

Page 409: ...or 1522 if VLAN tags are supported 15 6 Reserved must be cleared 5 FCE Flow control enable If asserted the receiver detects PAUSE frames Upon PAUSE frame detection the transmitter stops transmitting...

Page 410: ...transmission of data frames stopped MAC transmits a MAC Control PAUSE frame Next the MAC clears the TFC_PAUSE bit and resumes transmitting data frames If the transmitter pauses due to user assertion o...

Page 411: ...ause duration field The lower 16 bits of this register are not reset and you must initialize them Table 19 16 PALR Field Descriptions Field Description 31 0 PADDR1 Bytes 0 bits 31 24 1 bits 23 16 2 bi...

Page 412: ...0001 15 0 PAUSE_DUR Pause Duration field used in PAUSE frames Address 0xFC03_0118 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R IADDR1...

Page 413: ...may need to be modified to match a given system requirement worst case bus access latency by the transmit data DMA channel Address 0xFC03_0120 Access User read write 31 30 29 28 27 26 25 24 23 22 21 2...

Page 414: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFWR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figur...

Page 415: ...operation Address 0xFC03_0150 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 R_FSTART 0 0 W...

Page 416: ..._DES_START 0 0 W Reset Figure 19 23 Transmit Buffer Descriptor Ring Start Register ETDSR Table 19 27 ETDSR Field Descriptions Field Description 31 2 X_DES_START Pointer to start of transmit buffer des...

Page 417: ...roduced After the data DMA is complete and the DMA engine writes the buffer descriptor status bits hardware clears RxBD E or TxBD R to signal the buffer has been consumed Software may poll the BDs to...

Page 418: ...riable is written to the EMRBR register The driver RxBD software producer should set up some number of empty buffers for the Ethernet by initializing the address field and the E and W bits of the asso...

Page 419: ...tatus and length fields have been updated as required 1 The data buffer associated with this BD is empty or reception is currently in progress Offset 0 14 RO1 Receive software ownership This field is...

Page 420: ...received and the CRC check that occurred at the preceding byte boundary generated an error This bit is valid only if the L bit is set If this bit is set the CR bit is not set Offset 0 3 Reserved must...

Page 421: ...criptor is found at the location defined in ETDSR Offset 0 12 TO2 Transmit software ownership This field is reserved for use by software This read write bit is not modified by hardware nor does its va...

Page 422: ...ters reset when the ECR ETHER_EN bit is cleared which is accomplished by a hard reset or software to halt operation By clearing ECR ETHER_EN configuration control registers such as the TCR and RCR are...

Page 423: ...nly needed for full duplex flow control RCR TCR MSCR optional Clear MIB_RAM Table 19 33 FEC User Initialization Before ECR ETHER_EN Description Initialize FRSR optional Initialize EMRBR Initialize ERD...

Page 424: ...AC Table 19 35 shows these signals The 7 wire serial mode interface RCR MII_MODE cleared is generally referred to as AMD mode Table 19 36 shows the 7 wire mode connections to the external transceiver...

Page 425: ...cessary When all the frame data is transmitted FCS frame check sequence or 32 bit cyclic redundancy check CRC bytes are appended if the TC bit is set in the transmit frame control word If the ABC bit...

Page 426: ...FEC_RXDV is asserted the receiver first checks for a valid PA SFD header If the PA SFD is valid it is stripped and the receiver processes the frame If a valid PA SFD is not found the frame is ignored...

Page 427: ...ionally as shown in Figure 19 27 Otherwise if the DA is not a broadcast address then the microcontroller runs the address recognition subroutine as shown in Figure 19 28 If the DA is a group multicast...

Page 428: ...ch Pause Frame False False False False True True True True Receive Frame Receive Frame Receive Frame Receive Frame Reject Frame Reject Frame Set BC bit in RCV BD Set MC bit in RCV BD if multicast Set...

Page 429: ...lects a bit set in the hash table the frame is accepted otherwise it is rejected For example if eight group addresses are stored in the hash table and random group addresses are received the hash tabl...

Page 430: ...3 B5FF_FFFF_FFFF 0x4 4 95FF_FFFF_FFFF 0x5 5 D5FF_FFFF_FFFF 0x6 6 F5FF_FFFF_FFFF 0x7 7 DBFF_FFFF_FFFF 0x8 8 FBFF_FFFF_FFFF 0x9 9 BBFF_FFFF_FFFF 0xA 10 8BFF_FFFF_FFFF 0xB 11 0BFF_FFFF_FFFF 0xC 12 3BFF_...

Page 431: ...FFF_FFFF 0x29 41 1FFF_FFFF_FFFF 0x2A 42 3FFF_FFFF_FFFF 0x2B 43 BFFF_FFFF_FFFF 0x2C 44 9FFF_FFFF_FFFF 0x2D 45 DFFF_FFFF_FFFF 0x2E 46 EFFF_FFFF_FFFF 0x2F 47 93FF_FFFF_FFFF 0x30 48 B3FF_FFFF_FFFF 0x31 49...

Page 432: ...nsmit backoff timer hardware for tracking the appropriate collision backoff time in half duplex mode The pause timer increments once every slot time until OPD PAUSE_DUR slot times have expired On OPD...

Page 433: ...t time the retry process is initiated The transmitter waits a random number of slot times If a collision occurs after 512 bit times then no retransmission is performed and the end of frame buffer is c...

Page 434: ...t or signal quality error To signify a good self test the transceiver indicates a collision to the FEC within four microseconds after completion of a frame transmitted by the Ethernet controller This...

Page 435: ...e CRC error can be ignored if checking is not required 19 5 15 2 4 Frame Length Violation When the receive frame length exceeds MAX_FL bytes the BABR interrupt is generated and RxBD LG is set The fram...

Page 436: ...Fast Ethernet Controller FEC 19 44 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 437: ...ver For more details on the USB OTG module refer to Chapter 21 Universal Serial Bus Interface On The Go Module USB host modules must supply 500 mA with a 5 V supply on its downstream port referred to...

Page 438: ...n access via USBCLKIN is provided for an external USB reference clock 60MHz The USB host controller provides control and status signals to interface with external USB host power devices Use these cont...

Page 439: ...cted at connect time via sensing of the DP or DM pullup resistor on the connected device using procedures of enumeration in the USB network The USB host module provides the following modes of operatio...

Page 440: ...ck source USBH_DM I O D output of the dual speed transceiver for the USB Host module State Meaning Asserted Data 1 Negated Data 0 Timing Asynchronous USBH_DP I O D output of the dual speed transceiver...

Page 441: ...ware Parameters HWHOST N 32 R 0x1002_0001 21 3 1 3 21 11 0xFC0B_4010 TX Buffer Hardware Parameters HWTXBUF N 32 R 0x8004_0404 21 3 1 5 21 12 0xFC0B_4014 RX Buffer Hardware Parameters HWRXBUF N 32 R 0x...

Page 442: ...0_0000 21 3 3 9 21 26 0xFC0B_4160 Master Interface Data Burst Size BURSTSIZE N 32 R W 0x0000_0404 21 3 3 10 21 27 0xFC0B_4164 Host Transmit FIFO Tuning Control TXFILLTUNING N 32 R W 0x0002_0000 21 3 3...

Page 443: ...on the Enhanced Host Controller Interface Specification for Universal Serial Bus EHCI from Intel Corporation The USB OTG module can act as a host a device or an On The Go negotiable host device on the...

Page 444: ...rnal USB DP and DM cable signals for a USB 2 0 network Several USB system elements are not supported on the device as they are available via standard products from various manufacturers 21 1 2 Block D...

Page 445: ...I Allows direct connection of FS LS devices without an OHCI UHCI companion controller Supported by Linux and other commercially available operating systems USB device mode Supports full speed operatio...

Page 446: ...le is configured to use the on chip FS LS transceiver by default The OTG module also includes an interface to an optional external high speed ULPI PHY For high speed operation the external ULPI transc...

Page 447: ...ctionality of the USB OTG module NOTE The ULPI signals are multiplexed with the FEC module This section describes the signal functions when in ULPI mode refer to Chapter 13 General Purpose I O Module...

Page 448: ...example when PHY s PLL is not stable State Meaning Asserted PHY has data to transfer to the link Negated PHY has no data to transfer Timing Synchronous to USB_CLKIN or ULPI_CLK ULPI_NXT I Next data P...

Page 449: ...PPU Enables the 1 5K resistor pull up on DP R Y A Session Valid AVLD Indicates a valid session level for A device detected on VBUS R W N B Session Valid BVLD Indicates a valid session level for B devi...

Page 450: ...ster Length CAPLENGTH Y H D 8 R 0x40 21 3 2 2 21 13 0xFC0B_0104 Host Structural Parameters HCSPARAMS Y H 32 R 0x0001_0011 21 3 2 3 21 14 0xFC0B_0108 Host Capability Parameters HCCPARAMS Y H 32 R 0x000...

Page 451: ...PRIME N D 32 R W 0x0000_0000 21 3 3 18 21 39 0xFC0B_01B4 Endpoint De initialize EPFLUSH N D 32 R W 0x0000_0000 21 3 3 19 21 40 0xFC0B_01B8 Endpoint Status Register EPSR N D 32 R 0x0000_0000 21 3 3 20...

Page 452: ...0 0 0 0 0 0 0 0 SM PHYM PHYW 0 0 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 1 Figure 21 4 General Hardware Parameters Register HWGENERAL Table 21 6 HWGENERAL Field Desc...

Page 453: ...of supported transaction translator periodic contexts Always 0x10 0x10 16 23 16 TTASY Transaction translator contexts Number of transaction translator contexts Always 0x02 0x02 2 15 4 Reserved always...

Page 454: ...0 Store device transmit contexts in the TX FIFO 1 Store device transmit contexts in a register file 30 24 Reserved always cleared 23 16 TXCHANADD Transmit channel address Number of address bits requir...

Page 455: ...register 21 3 2 2 Capability Registers Length Register CAPLENGTH Register is used as an offset to add to the register base address to find the beginning of the operational register space the location...

Page 456: ...ators 23 20 N_PTT Ports per transaction translator Non EHCI field Indicates number of ports assigned to each transaction translator within host controller 19 17 Reserved always cleared 16 PI Port indi...

Page 457: ...tive to the current position of the executing host controller This field is always 0 0 The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of...

Page 458: ...24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HC DC 0 0 DEN W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 F...

Page 459: ...is a non EHCI bit 14 ATDTW Add dTD TripWire This is a non EHCI bit that is present on the USB OTG module only This bit is used as a semaphore when a dTD is added to an active primed endpoint This bit...

Page 460: ...is inactive Doing so yields undefined results This bit used only in host mode Writing a 1 to this bit when the USB OTG module is in device mode has undefined results 5 ASE Asynchronous schedule enable...

Page 461: ...an attached state before initiating a device controller reset all primed endpoints must be flushed and the USBCMD RS bit must be cleared 0 RS Run Stop Host mode USB Host and USB OTG When set the cont...

Page 462: ...ost controller halted This bit is cleared when the USBCMD RS bit is set The controller sets this bit after it stops executing because of the USBCMD RS bit being cleared by software or the host control...

Page 463: ...occurs depends on the frame list size For example if the frame list size as programmed in the USBCMD FS field is 1024 the frame index register rolls over every time FRINDEX 13 toggles Similarly if the...

Page 464: ...e OTG module only When this bit is set and the USBSTS SLI bit transitions USB OTG controller issues an interrupt Software writing a 1 to the USBSTS SLI bit acknowledges the interrupt Used only in devi...

Page 465: ...frame If FRINDEX 13 3 equals the SOF value FRINDEX 2 0 is incremented SOF for 125 sec microframe 3 FRE Frame list rollover enable When this bit and the USBSTS FRI bit are set controller issues an inte...

Page 466: ...escription 31 14 Reserved must be cleared 13 0 FRINDEX Frame index The value in this register increments at the end of each time frame microframe Bits N 3 are for the frame list current index This mea...

Page 467: ...gister In host mode it is the ASYNCLISTADDR register in device mode it is the EPLISTADDR register See Section 21 3 3 8 Endpoint List Address Register EPLISTADDR for more information Table 21 22 PERIOD...

Page 468: ...ield Description 31 5 ASYBASE Link pointer low LPL These bits correspond to memory address signal 31 5 This field may only reference a queue head QH Used only in host mode 4 0 Reserved must be cleared...

Page 469: ...red 30 24 TTHA TT Hub Address This field is used to match against the Hub Address field in a QH or siTD to determine if the packet is routed to the internal TT for directly attached FS LS devices If t...

Page 470: ...ffs Address 0xFC0B_0164 TXFILLTUNING Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 TXFIFOTHRES 0 0 0 TXSCHHEALTH TX...

Page 471: ...is register should limit the number of back off events captured in the TXSCHHEALTH field to less than 10 per second in a highly utilized bus Choosing a value too high for this register is not desired...

Page 472: ...ed in the USBSTS and USBINTR registers When a wake up or read write operation completes the ULPI interrupt is set Table 21 29 ULPI VIEWPORT Field Descriptions Field Description 31 ULPI_WU ULPI wake up...

Page 473: ...suspend and current connect status It is also used to initiate test mode or force signaling and allows software to place the PHY into low power suspend mode and disable the PHY clock Address 0xFC0B_0...

Page 474: ...tion Host mode USB host and USB OTG The PHY can be placed into low power suspend when downstream device is put into suspend mode or when no downstream device connects Software completely controls low...

Page 475: ...current setting of the port power control switch 0 equals off 1 equals on When power is not available on a port PP 0 it is non functional and does not report attaches detaches etc When an over current...

Page 476: ...esume duration is timed in the driver When the controller owns the port the resume sequence follows the defined sequence documented in the USB Specification Revision 2 0 The resume signaling full spee...

Page 477: ...ge until the port state actually changes There may be a delay in disabling or enabling a port due to other host and bus events When the port is disabled downstream propagation of data is blocked excep...

Page 478: ...nd timer interrupt enable 0 Disable 1 Enable 28 BSEIE B session end interrupt enable 0 Disable 1 Enable 27 BSVIE B session valid interrupt enable 0 Disable 1 Enable 26 ASVIE A session valid interrupt...

Page 479: ...MST 1 millisecond timer toggle This bit toggles once per millisecond 12 BSE B session end 0 VBus is above B session end threshold 1 VBus is below B session end threshold 11 BSV B Session valid 0 VBus...

Page 480: ...e TX latency fills to capacity before the packet launches onto the USB Time duration to pre fill the FIFO becomes significant when stream disable is active See TXFILLTUNING to characterize the adjustm...

Page 481: ...for the USB OTG module 01 Reserved 10 Device controller 11 Host controller default for the USB host module Note The USB OTG module must be initialized to the desired operating mode after reset Addres...

Page 482: ...1 to the corresponding bit when posting a new transfer descriptor to an endpoint Hardware automatically uses this bit to begin parsing for a new transfer descriptor from the queue head and prepare a...

Page 483: ...be cleared 3 0 ERBR Endpoint receive buffer ready One bit for each endpoint indicates status of the respective endpoint buffer The hardware sets this bit in response to receiving a command from a corr...

Page 484: ...0 0 0 0 0 0 0 0 RXE 0 0 0 RXT 0 RXS W Reset 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Figure 21 36 Endpoint Control 0 EPCR0 Table 21 39 EPCR0 Field Descriptions Field Description...

Page 485: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 RXE 0 RXI 0 RXT RXD RXS W RXR Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 21 37 Endpoint Control Registers EPCRn T...

Page 486: ...to synchronize the data PIDs between the host and device This bit is self clearing 5 RXI RX data toggle inhibit This bit is only for testing and should always be written as 0 Writing a 1 to this bit c...

Page 487: ...are similar to those in the EHCI specification and used to allow device responses to be queued for each of the active pipes in the device 21 4 3 FIFO RAM Controller The FIFO RAM controller is used for...

Page 488: ...3 3V I O power supply Readers are directed to section 7 1 5 1 of the USB 2 0 specification 21 5 Initialization Application Information 21 5 1 Host Operation Enhanced Host Controller Interface EHCI Sp...

Page 489: ...software must write the ASYNCLISTADDR register with the address of a control or bulk queue head Software must then enable the asynchronous schedule by setting the asynchronous schedule enable ASE bit...

Page 490: ...hrough the end of the buffer pointers longwords After a transfer is complete the dTD status longword updates in the dTD pointed to by the currentTD pointer While a packet is in progress the overlay ar...

Page 491: ...0x0C1 Buffer Pointer Page 0 Current Offset 0x101 Buffer Pointer Page 1 Reserved 0x141 Buffer Pointer Page 2 Reserved 0x181 Buffer Pointer Page 3 Reserved 0x1C1 Buffer Pointer Page 4 Reserved 0x201 Re...

Page 492: ...o retire the current dTD Setting this bit disables the zero length packet When the device is transmitting the hardware does not append any zero length packet When receiving it does not require a zero...

Page 493: ...ransfer Descriptors 21 5 2 2 1 Next dTD Pointer Offset 0x0 The next dTD pointer is used to point the device controller to the next dTD in the linked list Table 21 44 Multiple Mode Control longword Fie...

Page 494: ...transaction The maximum value software may store in the field is 5 4K 0x5000 This is the maximum number of bytes 5 page pointers can access Although possible to create a transfer up to 20K this assume...

Page 495: ...performed on this dTD The bit encodings are Bit Status Field Description 7 Active Set by software to enable the execution of transactions by the device controller 6 Halted Set by the device controlle...

Page 496: ...SBINTR to enable the desired interrupts For device operation setting UE UEE PCE URE and SLE is recommended For a list of available interrupts refer to Section 21 3 3 3 USB Interrupt Enable Register US...

Page 497: ...vision 2 0 Figure 21 41 depicts the state of a USB 2 0 device Figure 21 41 USB 2 0 Device States States powered attach defaultFS HS suspendFS HS are implemented in the USB OTG and they are communicate...

Page 498: ...ores by reading the EPSETUPSR register and writing the same value back to the EPSETUPSR register 2 Clear all the endpoint complete status bits by reading the EPCOMPLETE register and writing the same v...

Page 499: ...cal signaling to indicate remote wake up The ability of a device to signal remote wake up is optional The USB OTG is capable of remote wake up signaling When the USB OTG is reset remote wake up signal...

Page 500: ...nts required for device operation The only exception is that control endpoints must use both directions on a single endpoint number to function as a control endpoint Endpoint 0 for example is always a...

Page 501: ...register can ensure both stall bits are set at the same instant NOTE Any write to the EPCRn register during operational mode must preserve the endpoint type field perform a read modify write 21 5 3 3...

Page 502: ...dpoint 3 transmit direction is configured as a bulk pipe expect the host to send IN requests to that endpoint This USB OTG module prepares packets for each endpoint direction in anticipation of the ho...

Page 503: ...the device controller when the packets described in the transfer descriptor are completed Each dTD describes N packets to transfer according to the USB variable length transfer protocol The formula b...

Page 504: ...s larger than the total bytes field spanning across two or more dTDs Upon successful completion of the packet s described by the dTD the active bit in the dTD is cleared and the next pointer is follow...

Page 505: ...and execute status handshake phases NOTE After receiving a new setup packet status and or handshake phases may remain pending from a previous control sequence These should be flushed and de allocated...

Page 506: ...according to the device controller state 21 5 3 4 5 Isochronous Endpoint Operation Isochronous endpoints used for real time scheduled delivery of data and their operational model is significantly diff...

Page 507: ...e device controller hardware masks that prime start until the next frame boundary This behavior is hidden from the DCD but occurs so the device controller can match the dTD to a specific micro frame A...

Page 508: ...ler by at least two micro frames Isochronous Pipe Synchronization When it is necessary to synchronize an isochronous data pipe to the host the micro frame number FRINDEX register can act as a marker T...

Page 509: ...see Section 21 5 3 6 1 Software Link Pointers Figure 21 42 Endpoint Queue Head Diagram In addition to current and next pointers and the dTD overlay examined in Section 21 5 3 4 Packet Transfers the d...

Page 510: ...by the DCD A setup transfer does not use a dTD but instead stores the incoming data from a setup packet in an 8 byte buffer within the dQH Upon receiving notification of the setup packet the DCD shou...

Page 511: ...e status of each dTD to determine completed status 21 5 3 6 2 Building a Transfer Descriptor Before a transfer can be executed from the linked list a dTD must be built to describe the transfer Use the...

Page 512: ...nue to 6 6 Clear the USBCMD ATDTW bit 7 If status bit read in step 4 is 1 DONE 8 If status bit read in step 4 is 0 then go to case 1 step 1 21 5 3 6 4 Transfer Completion After a dTD is initialized an...

Page 513: ...tivity It is not desirable to have this wait loop within an interrupt service routine 3 Read the EPSR register to ensure that for all endpoints commanded to be flushed that the corresponding bits are...

Page 514: ...ned in the dQH mult field within the given micro frame For scheduled data delivery DCD may need to readjust the data queue because a fulfillment error causes the device controller to cease data transf...

Page 515: ...CI specification Device and OTG operation are not specified in the EHCI specification and thus the implementation supported in the USB OTG module is proprietary 21 5 5 1 Embedded Transaction Translato...

Page 516: ...It is demonstrated here how hub address and endpoint speed fields should be set for directly attached FS LS devices and hubs 1 QH for direct attach FS LS asynchronous bulk control endpoints periodic...

Page 517: ...ader is familiar with the EHCI and USB 2 0 transaction translator operational models Microframe Pipeline The EHCI operational model uses the concept of H frames and B frames to describe the pipeline b...

Page 518: ...acket babbles into SOF time USB 2 0 11 17 4 Transaction tracking for 2 data pipes USB 2 0 11 17 5 Clear_TT_Buffer capability provided though the use of the TTCTRL register Periodic Transaction Schedul...

Page 519: ...n the operation registers should always be written to zero This is an EHCI requirement of the device controller driver that must be adhered to Read operations by the module must properly mask EHCI res...

Page 520: ...ware shall clear the PORTSCn PR bit after 10 ms This step necessary in a standard EHCI design may be omitted with this implementation Should the EHCI host controller driver attempt to write a 0 to the...

Page 521: ...ller block diagram is shown below Figure 22 1 LCDC Block Diagram 22 1 2 Features The LCDC provides the following features Support for single non split screen monochrome or color LCD panels and self re...

Page 522: ...Panel interface of 12 16 18 bit for color panels For 4 bpp and 8 bpp a palette table is used for re mapping of data from memory independent of type of panel used For the 1 bpp 2 bpp 12 bpp 16 bpp and...

Page 523: ...cates start of next line LCD_LSCLK O Shift clock Clock for latching data into the display driver s internal shift register LCD_ACD LCD_OE O Passive matrix Alternate crystal direction Active matrix Out...

Page 524: ...Register LCD_ICR 32 R W 0x0000_0000 22 3 15 22 18 0xFC0A_C03C LCD Interrupt Enable Register LCD_IER 32 R W 0x0000_0000 22 3 16 22 19 0xFC0A_C040 LCD Interrupt Status Register LCD_ISR 32 R W 0x0000_00...

Page 525: ...22 has a fixed value for a picture s image 1 0 Reserved must be cleared Address 0xFC0A_C004 LCD_SR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4...

Page 526: ...idth Register LCD_VPW Table 22 6 LCD_VPW Field Descriptions Field Description 31 10 Reserved must be cleared 9 0 VPW Virtual page width Defines the virtual page width of the LCD panel The VPW bits rep...

Page 527: ...to LCD_SR XMAX 15 10 Reserved must be cleared 9 0 CYP Cursor Y position Indicates the cursor s vertical starting position in pixel count from 0 to LCD_SR YMAX Address 0xFC0A_C010 LCD_CWHB Access User...

Page 528: ...red 20 16 CH Cursor height Specifies the height of the hardware cursor in pixels This field can be any value between 1 and 31 Setting this field to zero disables the cursor 15 8 Reserved must be clear...

Page 529: ...component of the cursor color in color mode 0x00 No blue 0x3F Full blue Address 0xFC0A_C018 LCD_PCR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R TFT COL OR PBSIZ BPIX PIX...

Page 530: ...setting usage 0 The LCD panel is a monochrome display 1 The LCD panel is a color display 29 28 PBSIZ Panel bus width Specifies the panel bus width Applicable for monochrome or passive matrix color mon...

Page 531: ...ertical scan in reverse direction 15 ACDSEL LCD_ACD clock source select Selects the clock source used by the alternative crystal direction counter 0 Use LCD_FLM as clock source for ACD count 1 Use LCD...

Page 532: ...ved must be cleared 15 8 H_WAIT_1 Wait between LCD_OE and LCD_HSYNC In TFT mode this field specifies the number of LCD_LSCLK periods between the end of LCD_OE signal and the beginning of the LCD_HSYNC...

Page 533: ...CD_VSYNC pulse for active mode TFT 1 This field has no meaning in passive non color mode The actual delay is V_WAIT_1 lines In passive color mode this field is the delay measured in virtual clock peri...

Page 534: ...me For example in 4 bpp mode setting POS 16 shifts the data 16bits which equates to panning the image by 4 pixels to the left Note Use the LSSAR register to shift the data more than 32 bits or for 18...

Page 535: ...ng densities This field is programmable to any value between 0 and 16 0 and 16 are already defined as two of the four colors 3 0 GRAY1 Grayscale 1 Represents one of the two grayscale shading densities...

Page 536: ...0 Figure 22 14 LCD PWM Contrast Control Register LCD_PCCR Table 22 15 LCD_PCCR Field Descriptions Field Description 31 25 Reserved must be cleared 24 16 CLS_HI_ WIDTH LCD_CLS high pulse width Controls...

Page 537: ...st length is fixed 30 21 Reserved must be cleared 20 16 HM DMA high mark Establishes the high mark for DMA requests For dynamic burst length after the DMA request is made data is loaded and the pixel...

Page 538: ...must be cleared 0 SELF_REF Self refresh mode enable 0 Disable self refresh 1 Enable self refresh Address 0xFC0A_C038 LCD_ICR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1...

Page 539: ...T_CON Interrupt condition Determines if an interrupt condition is set at the beginning or the end of frame condition Refer to table in the INT_SYN field description for INTSYN INTCON setting usage 0 I...

Page 540: ...Reserved must be cleared 7 GWUDR Graphic window underrun error interrupt enable 0 Mask interrupt 1 Enable interrupt 6 GWERR Graphic window error response interrupt enable 0 Mask interrupt 1 Enable int...

Page 541: ...by reading the status register at power on reset or when the LCDC is disabled 0 Interrupt has not occurred 1 Interrupt has occurred 5 GWEOF Graphic window end of frame interrupt Indicates whether the...

Page 542: ...0 LCD_GWSAR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R GWSA 0 0 W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 543: ...graphic window size cannot be set to 0 Note The maximum supported panel size is 800x600 pixels Therefore the maximum value for this bit field is 0x258 Address 0xFC0A_C058 LCD_GWVPW Access User read wr...

Page 544: ...g the image by 4 pixels left Note Use the LGWSAR register to shift the data more than 32 bits or for 18 bpp panning To achieve panning of the final image by N bits Address 0xFC0A_C060 LCD_GWPR Access...

Page 545: ...lly opaque completely visible on the LCD screen 23 GWCKE Graphic window color keying enable Enable or disable graphic window color keying 0 Disable color keying of graphic window 1 Enable color keying...

Page 546: ...gnificant 12 or 18 bits NOTE Byte or word access to the RAM corrupts its contents Address 0xFC0A_C068 LCD_GWDCR Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...

Page 547: ...Because only four bits are used to encode the color a maximum of 16 colors can be selected out of a palette of 4096 The first 16 mapping RAM entries must be written to define the codes for the 16 avai...

Page 548: ...e eight bits are used to encode the color a maximum of 256 colors can be selected out of a palette of 256K All 256 mapping RAM entries must be written to define the codes for the 256 available combina...

Page 549: ...epresented by the shaded area in Figure 22 27 for display on the LCD panel The maximum page width is specified by the virtual page width VPW parameter Virtual page height VPH does not affect the LCDC...

Page 550: ...Similar to the screen the virtual page width graphic window start address and graphic window width and height are software programmable The position of the graphic window on screen is specified by th...

Page 551: ...the next frame A typical panning algorithm includes an interrupt at the beginning of the frame In the interrupt service routine POS and or SSA are updated the old values are internally latched The up...

Page 552: ...25 Bit 24 P6 P7 8 bpp Mode Byte Address Sample Bit to Pixel Mapping 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P0 1 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 P1 2 Bit 23 Bit 22 Bit...

Page 553: ...ffect may or may not be linearly related to the frame rate A logarithmic scale such as 0 1 4 1 2 and 1 might be more pleasing than a linearly spaced scale such as 0 5 16 11 16 and 1 for certain graphi...

Page 554: ...M is output to the FRC blocks that independently process the code corresponding to the red green and blue components of each pixel to generate the required shade and intensity For 4 bit and 8 bit acti...

Page 555: ...ure 22 33 Passive Matrix Color Pixel Generation 1 0 1 1 0 0 7 6 5 4 3 2 1 0 4 bpp Data 8 bpp Data 1 0 1 1 1 1 1 0 1 1 Color RAM Inside LCDC 256 rows R G B FRC FRC FRC 0 1 0 1 1 0 1 0 1 1 0 1 1 1 0 1 1...

Page 556: ...the frames The LCDC can generate 16 simultaneous gray scale levels Table 22 33 Gray Palette Density Gray Code Hexadecimal Density Density Decimal 0 0 0 1 1 8 0 125 2 1 5 0 2 3 1 4 0 25 4 1 3 0 333 5...

Page 557: ...ions on the device and must be configured for LCDC operation before they can be used 22 4 9 2 Passive Matrix Panel Interface Signals Figure 22 36 shows the LCD interface timing for monochrome panels a...

Page 558: ...umber of LCD_FLM pulses This signal refreshes the LCD panel NOTE The LCD_D bus width is programmable to 1 2 4 or 8 bits in monochrome mode the COLOR bit in the panel configuration register is set to 0...

Page 559: ...he width of the LCD_FLM pulse and H_WIDTH must be at least 1 H_WAIT_2 defines the delay from the end of LCD_LP to the beginning of data output NOTE All parameters are defined in unit of pixel clock pe...

Page 560: ...pulse LCD_HSYNC the LCD_LP pin in passive mode vertical sync pulse LCD_VSYNC the LCD_FLM pin in passive mode output enable LCD_OE the LCD_ACD pin in passive mode and line data LCD_D signals The seque...

Page 561: ...bit mode the LCD_D 17 14 bits define red the LCD_D 11 8 bits define green and the LCD_D 5 2 bits define blue In 16 bit mode the LCD_D 17 13 bits define red the LCD_D 11 6 bits define green and the LC...

Page 562: ...3 m m 1 239 240 LCD_HSYNC LCD_VSYNC LCD_HSYNC LINE 1 LINE 2 LINE 3 LINE 4 LINE n LINE 1 LCD_D8 G3 0 0 G3 0 1 G3 0 2 LCD_D7 G2 0 0 G2 0 1 G2 0 2 LCD_D6 G1 0 0 G1 0 1 G1 0 2 LCD_D5 G0 0 0 G0 0 1 G0 0 2...

Page 563: ...line period before LCD_VSYNC The LCD_HSYNC pulse is output during the V_WAIT_1 delay For V_WIDTH vertical sync pulse width 0 LCD_VSYNC encloses one LCD_HSYNC pulse For V_WIDTH 2 LCD_VSYNC encloses two...

Page 564: ...Liquid Crystal Display Controller LCDC 22 44 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 565: ...esigned to be used as a vehicle serial data bus meeting the specific requirements of this field real time processing reliable operation in the EMI environment of a vehicle cost effectiveness and requi...

Page 566: ...pare functions required for communicating on the CAN bus It can also provide protection against damage to the FlexCAN caused by a defective CAN bus or defective stations Figure 23 3 Typical CAN System...

Page 567: ...Independent of the transmission medium an external transceiver is assumed Open network architecture Multimaster bus High immunity to EMI Short latency time due to an arbitration scheme for high prior...

Page 568: ...g transmission or reception FlexCAN does the following Waits to be in idle or bus off state or else waits for the third bit of intermission and then checks it to be recessive Waits for all internal ac...

Page 569: ...us registers The upper 256 bytes are fully used for the message buffer structures as described in Section 23 3 9 Message Buffer Structure Table 23 1 FlexCAN Memory Map Address Register Width bits Affe...

Page 570: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 R MDIS FRZ 0 HALT NOT RDY 0 SOFT RST FRZ ACK SUPV 0 0 LPM ACK 0 0 0 0 W Reset 1 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0...

Page 571: ...he user should poll this bit to know when the soft reset has completed 0 Soft reset cycle completed 1 Soft reset cycle initiated 24 FRZACK Freeze acknowledge Indicates that the FlexCAN module has ente...

Page 572: ...n the clock source frequency set by CLK_SRC bit and the serial clock S clock frequency The S clock period defines the time quantum of the CAN protocol For the reset value the S clock frequency is equa...

Page 573: ...e Defines how FlexCAN recovers from bus off state If this bit is cleared automatic recovering from bus off state occurs according to the CAN Specification 2 0B If the bit is set automatic recovering f...

Page 574: ...FlexCAN to operate in listen only mode In this mode transmission is disabled all error counters are frozen and the module operates in a CAN error passive mode Only messages acknowledged by another CAN...

Page 575: ...ID 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB4 ID 0 0 0 0 0 0 1 1 1 1 1 0 MB5 ID 0 0 0 0 0 0 1 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB14 ID 1 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1...

Page 576: ...STAT is updated to reflect error passive state If the FlexCAN state is error passive and TXECTR or RXECTR decrements to a value less than or equal to 127 while the other already satisfies this conditi...

Page 577: ...23 3 6 FlexCAN Error and Status Register ERRSTAT ERRSTAT reflects various error conditions some general status of the device and is the source of three interrupts to the CPU The reported error conditi...

Page 578: ...Indicates whether an acknowledgment has been correctly received for a transmitted message 0 No ACK error was detected since the last read of this register 1 An ACK error was detected since the last r...

Page 579: ...If the CANCTRL BOFFMSK bit is set an interrupt request is generated This interrupt is not requested after reset 1 ERRINT Error interrupt Indicates that at least one of the ERRSTAT 15 10 bits is set Th...

Page 580: ...dentifier field for frame identification and up to 8 bytes of data Address 0xFC02_0030 IFLAG Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 581: ...nded identifier 18 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x0 CODE SRR IDE RTR LENGTH TIME STAMP 0x4 Standard ID 28 18 Extended ID 17 0 0x8 Data Byt...

Page 582: ...on 0 Indicates the current MB has a data frame to be transmitted 1 Indicates the current MB has a remote frame to be transmitted 19 16 LENGTH Length of data in bytes Indicates the length in bytes of t...

Page 583: ...cates OVERRUN but the CPU reads the C S word and then unlocks the MB when a new frame is written to the MB the code returns to FULL 0110 If the code already indicates OVERRUN and yet another new frame...

Page 584: ...00 is temporarily deactivated does not participate in the current arbitration matching run when the CPU writes to the C S field of that MB 23 3 11 Transmit Process The CPU prepares or changes an MB fo...

Page 585: ...nned to find the lowest ID or the lowest MB number depending on the CANCTRL LBUF bit NOTE If CANCTRL LBUF is cleared the arbitration considers not only the ID but also the RTR and IDE bits placed insi...

Page 586: ...ed unless the CPU reads the C S word of another MB Only a single MB is locked at a time The only mandatory CPU read operation is the one on the control and status word to assure data coherency The CPU...

Page 587: ...ding ID bit is don t care 23 3 15 Message Buffer Managing To maintain data coherency and FlexCAN proper operation the CPU must obey the rules described in Section 23 3 11 Transmit Process and Section...

Page 588: ...is a point in time until which the deactivation of a Tx MB causes it not to be transmitted end of move out After this point it is transmitted but no interrupt is issued and the CODE field is not upda...

Page 589: ...same ID as the remote frame that was transmitted When a remote frame is received by the FlexCAN the remote frame ID is compared to the IDs of all transmit message buffers programmed with a CODE of 10...

Page 590: ...PLL generated clocks The value of this bit should not be changed unless the module is in disable mode CANMCR MDIS bit is set The PRESDIV field controls a prescaler that generates the serial clock S c...

Page 591: ...m expects transitions to occur on the bus during this period Transmit Point A node in transmit mode transfers a new value to the CAN bus at this point Sample Point A node samples the bus at this point...

Page 592: ...source is selected and the module is enabled CANMCR MDIS bit cleared the FlexCAN automatically enters freeze mode In freeze mode the FlexCAN is un synchronized to the CAN bus the CANMCR register s HA...

Page 593: ...nt the FlexCAN attempts to synchronize with the CAN bus 23 4 1 Interrupts There are 19 interrupt sources for the FlexCAN module An interrupt for each of the 16 MBs Plus a combined interrupt for all 16...

Page 594: ...FlexCAN 23 30 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 595: ...onsists of separate transmit and receive circuits with FIFO registers and separate serial clock and frame sync generation for the transmit and receive sections The second set of Tx and Rx FIFOs replic...

Page 596: ...t the inter IC sound bus I2 S and the Intel AC97 standards Transmit Shift Reg 32 TXFIFO0 8x24 TXSR Internal Bus RXFIFO0 8x24 Receive Shift Reg SSI_RX0 RXSR Tx Clock Generator Tx Sync Generator Tx Cont...

Page 597: ...n network mode to provide two independent channels for transmission and reception Programmable data interface modes such as I2 S lsb msb aligned Programmable word length 8 10 12 16 18 20 22 or 24 bits...

Page 598: ...e the concept of a frame The beginning of the frame is marked with a frame sync when programmed with continuous clock The SSI_CCR DC bits determine length of the frame depending on whether data is bei...

Page 599: ...signal is referred to as the oversampling clock The frequency of SSI_MCLK is a multiple of the frame clock 24 2 4 SSI_FS Serial Frame Sync The input or output frame sync is used by the transmitter an...

Page 600: ...chronous SSI Configurations Continuous and Gated Clock Figure 24 3 shows an example of the port signals for an 8 bit data transfer Continuous and gated clock signals are shown as well as the bit lengt...

Page 601: ...1 0 x Gated clock in 1 1 1 x Gated clock out Table 24 4 SSI Memory Map Address Register Width bits Access Reset Value Section Page 0xFC0B_C000 SSI Transmit Data Register 0 SSI_TX0 32 R W 0x0000_0000...

Page 602: ...SSI_TX0 0xFC0B_C004 SSI_TX1 Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R SSI_TX W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 603: ...the SSI_TXD port The word length control bits SSI_CCR WL determine the number of bits to shift out of the TXSR before it is considered empty and can be written to again The data to be transmitted occu...

Page 604: ...egisters 0 and 1 SSI_RX0 1 The SSI_RX0 1 registers store the data received by the SSI For details on data alignment see Section 24 3 6 SSI Receive Shift Register RXSR SSI_TX 31 0 31 0 TXSR 12 bits 20...

Page 605: ...red to the appropriate SSI receive data register or receive FIFOs if the receive FIFO is enabled and the corresponding SSI_RX is full after a word has been shifted in For receiving less than 24 bits o...

Page 606: ...gure 24 12 Receive Data Path RXBIT0 1 RSHFD 0 lsb Alignment SSI_RX 31 0 12 bits 24 bits 20 bits 31 0 RXSR 24 bits 12 bits 20 bits 16 bits 7 11 15 7 11 15 16 bits SSI_RXD SSI_RX 31 0 31 0 24 bits 12 bi...

Page 607: ...ock idle state Controls the idle state of the transmit clock port SSI_BCLK and SSI_MCLK during internal gated clock mode 0 Clock idle state is 1 1 Clock idle state is 0 8 TCH Two channel operation ena...

Page 608: ...rruption 0 Receiver disabled 1 Receiver enabled 1 TE Transmitter Enables the transfer of the contents of the SSI_TX registers to the TXSR and also enables the internal transmit clock The transmit sect...

Page 609: ...RLS RFF1 RFF0 TFE1 TFE0 W Reset 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 Figure 24 15 SSI Interrupt Status Register SSI_ISR Table 24 8 SSI_ISR Field Descriptions Field Description 31 19 Reserved must be clear...

Page 610: ...tions Trigger Enabled SSI_IER RIE set SSI_IER RFF1 set SSI_ISR RFF1 sets Disabled SSI_IER RIE set SSI_IER RDR1 set SSI_RX1 loaded with new value Rx FIFO1 RDR1 is set when RDR1 is cleared during any of...

Page 611: ...mode When a transmit underrun error occurs the previous data is retransmitted In network mode each time slot requires data transmission unless masked through the SSI_TMASK register when the transmitte...

Page 612: ...ence of a receive frame sync during reception of the next word in SSI_RX registers Table 24 8 SSI_ISR Field Descriptions continued Field Description SSI Mode Transmit frame sync interrupt Required con...

Page 613: ...8 SSI_ISR Field Descriptions continued Field Description Last time slot interrupts Required conditions Trigger TLS SSI_IER TIE set SSI_IER TLS set SSI_ISR TLS sets RLS SSI_IER RIE set SSI_IER RLS set...

Page 614: ...20 19 18 17 16 R 0 0 0 0 0 0 0 0 0 RDMAE RIE TDMAE TIE CMD AU CMDU RXT W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R RDR1 RDR0 TDE1 TDE0 ROE1 ROE0 TUE1 TUE0 TFS RFS...

Page 615: ...a DMA request generates when either of the SSI_ISR TFE0 1 bits is set If the Tx FIFO is disabled a DMA request generates when either of the SSI_ISR TDE0 1 bits is set 0 SSI transmitter DMA requests d...

Page 616: ...direction and source of the clock signal on the SSI_BCLK pin Refer to Table 24 3 for details of clock port configuration 0 Clock is external 1 Clock generated internally 4 TSHFD Transmit shift direct...

Page 617: ...to receive the data word at bit position 0 or 15 31 in the receive shift register The shifting data direction can be msb or lsb first controlled by the RSHFD bit 0 msb aligned Shifting with respect t...

Page 618: ...bit clock period long 0 REFS Receive early frame sync Controls when the frame sync is initiated for the receive section The frame sync is disabled after one bit for bit length frame sync and after one...

Page 619: ...00000 provides continuous periodic data word transfer A bit length frame sync must be used in this case otherwise in word length mode the frame sync is always asserted 7 0 PM Prescaler modulus select...

Page 620: ...M1 Transmit FIFO empty watermark 1 Controls the threshold at which the SSI_ISR TFE1 flag is set The TFE1 flag is set when the data level in Tx FIFO 1 falls below the selected threshold 0001 TFE1 set w...

Page 621: ...set 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 24 21 SSI AC97 Control Register SSI_ACR Table 24 15 SSI_ACR Field Descriptions Field Description 31 11 Reserved must be clear...

Page 622: ...0 AC97 fixed mode 1 AC97 variable mode 0 AC97EN AC97 mode enable Refer to Section 24 4 1 5 AC97 Mode for details of AC97 operation 0 AC97 mode disabled 1 AC97 mode enabled Address 0xFC0B_C03C SSI_ACAD...

Page 623: ...e due to an update the SSI_ISR CMDDU bit is set During an AC97 read command 0x0_0000 in time slot 2 Address 0xFC0B_C044 SSI_ATAG Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 624: ...transmit time slot has been masked in the current frame Each bit corresponds to the respective time slot in the frame If a change is made to the register contents the transmission pattern is updated...

Page 625: ...ata register SSI_TX0 4 Transmitter enabled TE 1 5 Frame sync active for continuous clock case 6 Bit clock begins for gated clock case When the above conditions occur in normal mode the next data word...

Page 626: ...27 shows transmitter and receiver timing for an 8 bit word with two words per time slot in normal mode and continuous clock with a late word length frame sync The Tx data register is loaded with the d...

Page 627: ...divided into more than one time slot During each time slot one data word can be transferred rather than in the frame sync time slot as in normal mode Each time slot is then assigned to an appropriate...

Page 628: ...1 and FIFO 0 alternately Time slots are selected through the transmit and receive time slot mask registers SSI_TMASK and SSI_RMASK 24 4 1 2 1 Network Mode Transmit The transmit portion of SSI is enabl...

Page 629: ...s a receive interrupt to occur if the the RIE bit is set The second data word second time slot in the frame begins shifting in immediately after the transfer of the first data word to the SSI_RX regis...

Page 630: ...time slot If the FIFO is disabled RDR flag sets and causes a receiver interrupt if the RE RIE and SSI_IER RDR bits are set If the FIFO is enabled the RFF flag generates interrupts this flag is set in...

Page 631: ...ck mode presence of the clock indicates that valid data is on the SSI_TXD or SSI_RXD signals For this reason no frame sync is needed in this mode After transmission of data completes the clock is pull...

Page 632: ...clear all DC bits when the module is used in gated mode For gated clock operated in external clock mode proper clock signalling must apply to SSI_BCLK for it to function properly If the SSI uses risi...

Page 633: ...iant to I2 S bus specification from Philips Semiconductors February 1986 Revised June 5 1996 Figure 24 35 depicts basic I2 S protocol timing Figure 24 35 I2 S Mode Timing Serial Clock Frame Sync and S...

Page 634: ...forms these settings when in I2 S master mode Network mode is selected SSI_CR NET 1 Tx frame sync length set to one word long frame SSI_TCR TFSL 0 Rx frame sync length set to one word long frame SSI_R...

Page 635: ...st of the slots in that frame are all 20 bits wide The same sequence is followed while receiving data Refer to the AC97 specification for details regarding transmit and receive sequences and data form...

Page 636: ...e always 20 bits wide 2 Select the number of time slots through the SSI_CCR DC bits For AC97 operation the DC bits should be set to a value of 0xC resulting in 13 time slots per frame 3 Write data to...

Page 637: ...SSI module at frequencies that would not be achievable if standard internal core clock frequencies 180 or 240 MHz are used This is also the output master clock SSI_MCLK when in master mode Bit clock S...

Page 638: ...ation A programmable frame rate divider and a word length divider are used for frame rate sync signal generation Figure 24 37 shows a block diagram of the clock generator for the transmit section The...

Page 639: ...SSI_CLOCK is 12 MHz A 16 bit word network mode with DC 1 PM 1 the PSR 0 DIV2 1 a bit clock rate of 12 14 2 1 5 MHz is generated Because the 16 bit word rate equals two sampling rate or frame sync rat...

Page 640: ...onized with the rising edge of external clock signal SSI_BCLK 24 4 4 Supported Data Alignment Formats The SSI supports three data formats to provide flexibility with managing data These formats dictat...

Page 641: ...is useful when data is stored in a fixed point integer format which implies fractional values Table 24 24 Data Alignment Format Bit Number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 1...

Page 642: ...condition Reading the SSI_RX registers clears the RDR bits thus clearing the pending interrupt Two receive data interrupts two per channel in two channel mode are available receive data with exceptio...

Page 643: ...ontrol bits including those in SSI_CR are unaffected The SSI reset is useful for selective reset of the SSI without changing the present SSI control bits and without affecting the other peripherals Th...

Page 644: ...ol Register Bit SSI_CR 9 CIS 8 TCH 7 MCE 6 5 I2S 4 SYN 3 NET SSI_IER 22 RDMAE 20 TDMAE SSI_RCR SSI_TCR 9 RXBIT0 and TXBIT0 8 RFEN1 and TFEN1 7 RFEN0 and TFEN0 6 TFDIR 5 RXDIR and TXDIR 4 RSHFD and TSH...

Page 645: ...iscusses how to operate and program the real time clock RTC module that maintains a time of day clock provides stopwatch alarm and interrupt functions and supports the following features RTC Module Pr...

Page 646: ...ontains the 6 bit minutes counter and 5 bit hours counter RTC_DAYS contains the 16 bit day counter Alarm There are three alarm registers that mirror the three counter registers An alarm is set by acce...

Page 647: ...defined 25 3 1 25 3 0xFC0A_8004 RTC Seconds Counter Register RTC_SECONDS 32 R W Undefined 25 3 2 25 4 0xFC0A_8008 RTC Hours and Minutes Alarm Register RTC_ALRM_HM 32 R W 0x0000_0000 25 3 3 25 4 0xFC0A...

Page 648: ...cleared 5 0 MINUTES Current minutes Set to any value between 0 and 59 0x3B Address 0xFC0A_8004 RTC_SECONDS Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 649: ...and 59 0x3B Address 0xFC0A_800C RTC_ALRM_SEC Access User read write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 650: ...32 768 kHz 01 Input crystal frequency is 32 kHz 10 Input crystal frequency is 38 4 kHz 11 Input crystal frequency is 32 768 kHz 4 1 Reserved must be cleared 0 SWR Software reset Resets the module to...

Page 651: ...r 0 No interrupt has occurred 1 A day interrupt has occurred 2 ALM Alarm interrupt flag Indicates the real time clock matches the value in the alarm registers The alarm reoccurs every 65 536 days For...

Page 652: ...led 1 1 Hz interrupt enabled 3 DAY Day interrupt enable 0 Interrupt disabled 1 Day interrupt enabled 2 ALM Alarm interrupt enable 0 Interrupt disabled 1 Alarm interrupt enabled 1 MIN Minute interrupt...

Page 653: ...HOURMIN register so the average tolerance of the count is 0 5 minutes For better accuracy enable the stopwatch by polling the RTC_ISR MIN bit or via the minute interrupt service routine Note Write the...

Page 654: ...gnal when each of the four counters increments and can indicate when a counter rolls over For example each tick of the seconds counter causes the 1HZ interrupt flag to set When the seconds counter rol...

Page 655: ...It can generate an interrupt on a minute boundary For example to turn off the LCD controller after five minutes of inactivity program a value of 0x04 into RTC_STPWCH CNT At each minute the value in t...

Page 656: ...hanging the alarm or time of day day hour minute and second registers Figure 25 13 Flow Chart of Alarm and Time of Day Programming Configure RTC_CR Configure RTC_DAYS Configure RTC_SECONDS Configure R...

Page 657: ...le period and duty cycle With a suitable low pass filter the PWM can be used as a digital to analog converter Figure 26 1 PWM Block Diagram Internal Bus Clock fsys 3 Clock select PWM Clocks Period and...

Page 658: ...ry map for the PWM is shown below NOTE Longword accesses to any of the PWM registers result in a bus error Only byte and word accesses are allowed Table 26 1 PWM Memory Map Address1 2 Register Width b...

Page 659: ...26 2 PWME Field Descriptions Field Description 7 PWME7 PWM Channel 7 Enable In normal mode if enabled the PWM signal becomes available at PWMOUT7 when its corresponding clock source begins its next cy...

Page 660: ...select is changed while a PWM signal is being generated a truncated or stretched pulse can occur during the transition Address 0xFC09_0021 PWMPOL Access User Read Write 7 6 5 4 3 2 1 0 R PPOL7 0 PPOL5...

Page 661: ...t clock rates are generated The even numbered channels clock select has no effect when the corresponding PWMCTL CONn n 1 bit is set For example if PWMCTL CON01 equals 1 PWMCLK PCLK0 has no affect 6 4...

Page 662: ...ion 3 Reserved must be cleared 2 0 PCKA Clock A prescaler select These three bits control the rate of Clock A which can be used for PWM channels 1 and 5 Address 0xFC09_0024 PWMCAE Access User Read Wri...

Page 663: ...ed The channel 5 clock select polarity center align enable and enable bits control this concatenated output 5 CON23 Concatenates PWM channels 2 and 3 to form one 16 bit PWM channel 0 Channels 2 and 3...

Page 664: ...w scale value PWMSCLB Address 0xFC09_0028 PWMSCLA Access User Read Write 7 6 5 4 3 2 1 0 R SCALEA W Reset 0 0 0 0 0 0 0 0 Figure 26 8 PWM Scale A Register PWMSCLA Table 26 8 PWMSCLA Field Descriptions...

Page 665: ...d period registers with values from the buffers and the output to change according to the polarity bit The counter is also cleared at the end of the effective period see Section 26 3 2 5 Left Aligned...

Page 666: ...cle high time as a percentage of period for a particular channel Eqn 26 4 Table 26 10 PWMCNTn Field Descriptions Field Description 7 0 COUNT Current value of the PWM up counter Resets to zero when wri...

Page 667: ...TY6 0xFC09_0043 PWMDTY7 Access User Read Write 7 6 5 4 3 2 1 0 R DUTY W Reset 1 1 1 1 1 1 1 1 Figure 26 12 PWM Duty Registers PWMDTYn Table 26 12 PWMDTYn Field Descriptions Field Description 7 0 DUTY...

Page 668: ...input 6 IE PWM interrupt enable An interrupt is triggered to the device s interrupt controller when PWMSDN IF is set 0 Interrupt is disabled 1 Interrupt is enabled 5 RESTART PWM restart After setting...

Page 669: ...ls are disabled PWMEn 0 Clock A and B are scaled values of the input clock The value is software selectable for clock A and B and has options of 1 1 2 or 1 128 times the internal bus clock The value s...

Page 670: ...ing rates the counter would have to count down to 0x01 before counting at the proper rate Forcing the associated counter to re load the scale register value every time PWMSCLA or PWMSCLB is written pr...

Page 671: ...t the associated PWM channel output is high at the beginning of the waveform then goes low when the duty count is reached Conversely if the polarity bit is zero the output starts low and then goes hig...

Page 672: ...od registers with values from the buffers and the output to change according to the polarity bit When the channel is disabled PWMEn 0 the counter stops When a channel becomes enabled PWMEn 1 the assoc...

Page 673: ...the period register minus 1 NOTE Changing the PWM output mode from left aligned to center aligned output or vice versa while channels are operating can cause irregularities in the PWM output It is re...

Page 674: ...and reaches zero the counter direction changes from a down count back to an up count and a load from the double buffer period and duty registers to the associated registers is performed as described...

Page 675: ...concatenated channel 2 registers become the high order bytes of the double byte channel When channels 0 and 1 are concatenated channel 0 registers become the high order bytes of the double byte chann...

Page 676: ...s for the PWM regardless of the output mode left or center aligned and 8 bit normal or 16 bit concatenation Table 26 15 16 bit Concatenation Mode Summary CONnn PWMEn PPOLn PCLKn CAEn PWMn Output CON67...

Page 677: ...MPERn PPOLn PWMn Output 0x00 indicates no duty 0x00 1 Always Low 0x00 indicates no duty 0x00 0 Always High XX 0x001 indicates no period 1 Counter 0x00 and does not count 1 Always High XX 0x001 indicat...

Page 678: ...Pulse Width Modulation PWM Module 26 22 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 679: ...to operate normally In doze mode with the WCR DOZE bit set the watchdog timer module operation stops In doze mode with the WCR DOZE bit cleared the watchdog timer continues to operate normally Watchd...

Page 680: ...ndefined register bits are reserved for expansion Write accesses to these reserved address spaces and reserved register bits have no effect Register Width bits Access Reset Value Section Page Supervis...

Page 681: ...e 1 HALTED Halted mode bit Controls the function of the watchdog timer in halted debug mode After written the HALTED bit is not affected by further writes except in halted mode During halted mode watc...

Page 682: ...fter written the WM 15 0 field is not affected by further writes except in halted mode Writing to WMR immediately loads the new modulus value into the watchdog counter The new value is also used at th...

Page 683: ...WDR bit and asserts a system reset Both writes must occur in the order listed before the timeout but any number of instructions can be executed between the two writes However writing any value other t...

Page 684: ...Watchdog Timer Module 27 6 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 685: ...ee running down counter 28 1 2 Block Diagram Figure 28 1 PIT Block Diagram 28 1 3 Low Power Mode Operation This subsection describes the operation of the PIT modules in low power modes and debug mode...

Page 686: ...PIT continues to operate in its pre debug mode state but any updates made in debug mode remain 28 2 Memory Map Register Definition This section contains a memory map see Table 28 2 and describes the r...

Page 687: ...ess locations have no effect and result in a cycle termination transfer error 2 User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error Address...

Page 688: ...ars DBG During debug mode register read and write accesses function normally When debug mode is exited timer operation continues from the state it was in before entering debug mode but any updates mad...

Page 689: ...read write reload bit enables loading the value of PMRn into PIT counter when the count reaches 0x0000 0 Counter rolls over to 0xFFFF on count of 0x0000 1 Counter reloaded from PMRn on count of 0x0000...

Page 690: ...tch 28 3 2 Free Running Timer Operation This mode of operation is selected when the PCSRn RLD bit is clear In this mode the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus...

Page 691: ...s clock period as selected by the PCSRn PRE bits The PMRn PM bits select the timeout period Eqn 28 1 28 3 4 Interrupt Operation Table 28 6 shows the interrupt request generated by the PIT The PIF flag...

Page 692: ...Programmable Interrupt Timers PIT0 PIT3 28 8 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 693: ...Each DMA timer module has a separate register set for configuration and control The timers can be configured to operate from the internal bus clock or from an external clocking source using the DTnIN...

Page 694: ...Free run and restart modes Programmable interrupt or DMA request on input capture or reference compare DMA Timer Divider DMA Timer Mode Register DTMRn Prescaler Mode Bits DMA Timer Counter Register DT...

Page 695: ...A Timer n Extended Mode Register DTXMRn 8 R W 0x00 29 2 2 29 4 0xFC07_0003 0xFC07_4003 0xFC07_8003 0xFC07_C003 DMA Timer n Event Register DTERn 8 R W 0x00 29 2 3 29 5 0xFC07_0004 0xFC07_4004 0xFC07_80...

Page 696: ...on 1 Enable DMA request or interrupt upon reaching the reference value 3 FRR Free run restart 0 Free run Timer count continues incrementing after reaching the reference value 1 Restart Timer count is...

Page 697: ...ally clears the REF and CAP flags via the internal DMA ACK signal Table 29 3 DTXMRn Field Descriptions Field Description 7 DMAEN DMA request Enables DMA request output on counter reference match or ca...

Page 698: ...to REF clears the event condition Writing a 0 has no effect 0 CAP Capture event The counter value has been latched into DTCRn Writing a 1 to CAP clears the event condition Writing a 0 has no effect RE...

Page 699: ...2 1 0 R REF 32 bit reference value W Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 29 5 DTRRn Registers Table 29 5 DTRRn Field Descriptions Field Description 31 0 REF R...

Page 700: ...ses a defined DTnIN transition The capture edge bits DTMRn CE select the type of transition that triggers the capture and sets the timer event register capture event bit DTERn CAP If DTERn CAP and DTX...

Page 701: ...disable interrupt or DMA request on counter reference match or capture edge The DTMRn CLK register is configured to select the clock source to be routed to the prescaler Internal bus clock can be divi...

Page 702: ...x0000 move b 0x03 D0 writing ones to TER0 REF CAP move b D0 TER0 clears the event flags move w TMR0 D0 save the contents of TMR0 while setting bset 0 D0 the 0 bit This enables timer 0 and starts count...

Page 703: ...29 11 For example if a 80 MHz timer clock is divided by 16 DTMRn PS equals 0x7F and the timer is referenced at 0x1312C 78 124 decimal the time out period is Eqn 29 2 Timeout period 1 80 10 6 16 127 1...

Page 704: ...DMA Timers DTIM0 DTIM3 29 12 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 705: ...Figure 30 1 QSPI Block Diagram Queue Control Block Queue Pointer 4 Done Comparator End Queue Pointer Status Regs Delay Counter Control Logic Control Regs 80 byte QSPI RAM Chip Selects Command Divide b...

Page 706: ...pinned out Baud rates from 156 9 Kbps to 20 Mbps at 80 MHz internal bus frequency Programmable delays before and after transfers Programmable QSPI clock phase and polarity Supports wraparound mode for...

Page 707: ...lock QSPI_CLK Actively driven Clock output from QSPI Peripheral chip selects QSPI_CSn Actively driven Peripheral selects from QSPI Table 30 2 QSPI Memory Map Address1 1 Addresses not assigned to a reg...

Page 708: ...of QSPI_CLK is logic level 1 8 CPHA Clock phase Defines the QSPI_CLK clock phase 0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK 1 Data changed on the lea...

Page 709: ...mmand RAM The QSPI clears this bit automatically when a transfer completes The user can also clear this bit to abort transfer unless QIR ABRTL is set The recommended method for aborting transfers is t...

Page 710: ...n Determines where the QSPI wraps to in wraparound mode 0 Wrap to RAM entry zero 1 Wrap to RAM entry pointed to by QWR NEWQP 12 CSIV QSPI_CS inactive level 0 QSPI chip select outputs return to zero wh...

Page 711: ...d 12 ABRTL Abort lock out When set QDLYR SPE cannot be cleared by writing to the QDLYR QDLYR SPE is only cleared by the QSPI when a transfer completes 11 WCEFE Write collision WCEF interrupt enable 0...

Page 712: ...mand field provides transfer operations Address 0xFC05_C010 QAR Access User read write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 ADDR W Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3...

Page 713: ...must be set to control the level that the chip selects return to after the first transfer 14 BITSE Bits per transfer enable 0 Eight bits 1 Number of bits set in QMR BITS 13 DT Delay after transfer ena...

Page 714: ...and in the queue The internal pointer is initialized to the same value as QWR NEWQP During normal operation the following sequence repeats 1 The command pointed to by the internal pointer is executed...

Page 715: ...and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data 16 words of receive data and 16 bytes of commands A write to QDR ca...

Page 716: ...QSPI_CS signal levels for the transfer The command control field provides transfer options A maximum of 16 commands can be in the queue Queue execution proceeds from the address in QWR NEWQP through t...

Page 717: ...SPI_CLK period is used The command RAM delay after transmit enable bit QCR DT enables the programmable delay period from the negation of the QSPI_CS signals until the start of the next transfer The de...

Page 718: ...mitted Data that is simultaneously received is stored at the pointer address in receive RAM When the proper number of bits has been transferred the QSPI stores the working queue pointer value in QWR C...

Page 719: ...queue of 12 transfers All three QSPI_CS signals are used in this example 1 Write the QMR with 0xB308 to set up 12 bit data words with the data shifted on the falling clock edge and a QSPI_CLK frequen...

Page 720: ...Queued Serial Peripheral Interface QSPI 30 16 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 721: ...d for an external UART clock As Figure 31 1 shows each UART module interfaces directly to the CPU and consists of Serial communication channel Programmable clock generation Interrupt control logic and...

Page 722: ...sts for servicing See Section 31 4 2 2 Receiver NOTE The GPIO module must be configured to enable the peripheral function of the appropriate pins refer to Chapter 13 General Purpose I O Module prior t...

Page 723: ...equest asserted to the CPU or a DMA request Table 31 1 UART Module External Signals Signal Description UnTXD Transmitter Serial Data Output UnTXD is held high mark condition when the transmitter is di...

Page 724: ...C06_0010 0xFC06_4010 0xFC06_8010 UART Input Port Change Register UIPCRn 8 R See Section 31 3 8 31 12 UART Auxiliary Control Register UACRn 8 W 0x00 31 3 9 31 13 0xFC06_0014 0xFC06_4014 0xFC06_8014 UAR...

Page 725: ...h Transmitter RTS control is configured in UMR2n TXRTS 0 The receiver has no effect on UnRTS 1 When a valid start bit is received UnRTS is negated if the UART s FIFO is full UnRTS is reasserted when t...

Page 726: ...a bits per character to be sent The values shown do not include start parity or stop bits 00 5 bits 01 6 bits 10 7 bits 11 8 bits Address 0xFC06_0000 UMR20 0xFC06_4000 UMR21 0xFC06_8000 UMR22 Access U...

Page 727: ...o send operation The transmitter checks the state of UnCTS each time it is ready to send a character If UnCTS is asserted the character is sent if it is deasserted the signal UnTXD remains in the high...

Page 728: ...or force parity the corresponding character in the FIFO was received with incorrect parity If UMR1n PM equals 11 multidrop PE stores the received address or data A D bit PE is valid only when RXRDY i...

Page 729: ...haracters received when the FIFO is full are lost 0 RXRDY Receiver ready 0 The CPU has read the receive buffer and no characters remain in the FIFO after this read 1 One or more characters were receiv...

Page 730: ...SABLE when reconfiguring the receiver 011 RESET TRANSMITTER Immediately disables the transmitter and clears USRn TXEMP TXRDY No other registers are altered Because it places the transmitter in a known...

Page 731: ...this command has no effect 10 TRANSMITTER DISABLE Terminates transmitter operation and clears USRn TXEMP TXRDY If a character is being sent when the transmitter is disabled transmission completes befo...

Page 732: ...is cleared and the transmitter is disabled have no effect on the transmit buffer Figure 31 9 shows UTBn TB contains the character in the transmit buffer 31 3 8 UART Input Port Change Registers UIPCRn...

Page 733: ...e of state longer than 25 50 s occurred on the UnCTS input UACRn can be programmed to generate an interrupt to the CPU when a change of state is detected 3 1 Reserved 0 CTS Current state of clear to s...

Page 734: ...o report Section 31 3 5 UART Command Registers UCRn describes the RESET BREAK CHANGE INTERRUPT command 1 The receiver detected the beginning or end of a received break 1 FFULL RXRDY Status of FIFO or...

Page 735: ...UBG1n and UBG2n are write only and cannot be read by the CPU 31 3 12 UART Input Port Register UIPn The UIPn registers show the current state of the UnCTS input Address 0xFC06_0018 UBG10 0xFC06_4018 UB...

Page 736: ...tions Field Description 7 1 Reserved 0 CTS Current state of clear to send The UnCTS value is latched and reflects the state of the input pin when UIPn is read Note This bit has the same function and v...

Page 737: ...mmed in the UCSR Figure 31 17 Clocking Source Diagram NOTE If DTnIN is a clocking source for the timer or UART that timer module cannot use DTnIN for timer input capture 31 4 1 2 Calculating Baud Rate...

Page 738: ...31 18 Transmitter and Receiver Functional Diagram 31 4 2 1 Transmitter The transmitter is enabled through the UART command register UCRn When it is ready to accept a character UART sets USRn TXRDY Th...

Page 739: ...esume operation after a disable or software reset If the clear to send operation is enabled UnCTS must be asserted for the character to be transmitted If UnCTS is negated in the middle of a transmissi...

Page 740: ...ty if any is assembled and one stop bit is detected Data on the UnRXD input is sampled on the rising edge of the programmed clock source The lsb is received first The data then transfers to a receiver...

Page 741: ...the Rx FIFO and sets USRn RB RXRDY Figure 31 20 shows receiver functional timing Figure 31 20 Receiver Timing Diagram 31 4 2 3 FIFO The FIFO is used in the UART s receive buffer logic The FIFO consist...

Page 742: ...ve buffer is read The USRn should be read before reading the receive buffer If all three receiver holding registers are full a new character is held in the receiver shift register until space is avail...

Page 743: ...er and checking data assembled by the receiver to ensure proper operations Figure 31 22 Local Loopback Features of this local loopback mode are Transmitter and CPU to receiver communications continue...

Page 744: ...er notifies its respective CPU by setting USRn RXRDY and generating an interrupt if programmed to do so Each slave station CPU then compares the received address to its station address and enables its...

Page 745: ...receiver is enabled all received characters are transferred to the CPU through the receiver holding register during read operations In either case data bits load into the data portion of the FIFO whi...

Page 746: ...d checks for the following errors Transmitter never ready Receiver never ready Parity error Incorrect character received I O driver routine This routine See Sheet 4 p 31 32 and Sheet 5 p 31 33 consist...

Page 747: ...ve DMA request signal is asserted when the FIFO full or receive ready FFULL RXRDY flag in the interrupt status register UISRn FFULL RXRDY is set When the receive DMA request signal is asserted the DMA...

Page 748: ...eration of receiver ready to send RXRTS bit a Select receiver ready or FIFO full notification RXRDY FFULL bit b Select character or block error mode ERR bit c Select parity mode and type PM and PT bit...

Page 749: ...gure 31 25 UART Mode Programming Flowchart Sheet 1 of 5 Serial Module SINIT Initiate Channel Interrupts CHK1 Call CHCHK Save Channel Status Enable Any Errors Y N Enable Receiver Assert Request To Send...

Page 750: ...ace Channel In Local Loopback Mode Enable Transmitter Clear Status Word TxCHK Is Transmitter Ready Y N SNDCHR RxCHK Send Character To Transmitter Has Character Been Received N Y A Waited Too Long N N...

Page 751: ...5 A B B FRCHK Have Framing Error Set Framing Error Flag PRCHK Have Parity Error Set Parity Error Flag Get Character From Receiver Same As Transmitted Character Set Incorrect Character Flag N N Y CHRC...

Page 752: ...KI N Clear Change in Break Status Bit ABRKI1 N Has End of break IRQ Arrived Yet Y Y Clear Change in Break Status Bit Remove Break Character From Receiver FIFO Replace Return Address On System Stack An...

Page 753: ...UART Modules Freescale Semiconductor 31 33 Figure 31 25 UART Mode Programming Flowchart Sheet 5 of 5 OUTCH Is Transmitter Ready N Y Send Character To Transmitter Return MCF5329 Reference Manual Rev 3...

Page 754: ...UART Modules 31 34 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 755: ...interaction of the registers described in Section 32 2 Memory Map Register Definition Figure 32 1 I2 C Module Block Diagram Address Compare In Out Data Shift Start Stop Input Sync Clock Control Regist...

Page 756: ...sly This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly line computer NOT...

Page 757: ...s Register I2ADR R W 0x00 32 2 1 32 3 0xFC05_8004 I2 C Frequency Divider Register I2FDR R W 0x00 32 2 2 32 3 0xFC05_8008 I2 C Control Register I2CR R W 0x00 32 2 3 32 4 0xFC05_800C I2 C Status Registe...

Page 758: ...I2CR Access User read write 7 6 5 4 3 2 1 0 R IEN IIEN MSTA MTX TXAK RSTA 0 0 W Reset 0 0 0 0 0 0 0 0 Figure 32 4 I2 C Control Register I2CR IC Divider IC Divider IC Divider IC Divider 0x00 28 0x10 28...

Page 759: ...MSTA is cleared without generating a STOP signal 0 Slave mode Changing MSTA from 1 to 0 generates a STOP and selects slave mode 1 Master mode Changing MSTA from 0 to 1 signals a START on the bus and...

Page 760: ...mit cycle I2C_SDA sampled low when the master drives high during the acknowledge bit of a data receive cycle A start cycle is attempted when the bus is busy A repeated start cycle is requested in slav...

Page 761: ...ata transfer each data transfer can be several bytes long and awakens all slaves Address 0xFC05_8010 I2DR Access User read write 7 6 5 4 3 2 1 0 R DATA W Reset 0 0 0 0 0 0 0 0 Figure 32 6 I2C Data I O...

Page 762: ...nt by the calling master Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high as Figure 32 7 shows I2C_SCL is pulsed once for each data bit with the msb being se...

Page 763: ...ate a STOP or START signal Figure 32 9 32 3 5 STOP Signal The master can terminate communication by generating a STOP signal to free the bus A STOP signal is defined as a low to high transition of I2C...

Page 764: ...eleasing the bus The master transmits data to the slave first and then the master reads data from slave by reversing the R W bit Figure 32 11 Data Transfer Combined Format 1 2 3 4 5 6 7 8 1 2 5 6 7 8...

Page 765: ...ate during this time see Figure 32 12 When all devices concerned have counted off their low period the synchronized clock I2C_SCL line is released and pulled high At this point the device clocks and t...

Page 766: ...Divider Register I2FDR 2 Update the I2ADR to define its slave address 3 Set I2CR IEN to enable the I2 C bus interface system 4 Modify the I2CR to select or deselect master slave mode transmit receive...

Page 767: ...unction is disabled Polling should monitor IIF rather than ICF because that operation is different when arbitration is lost When an interrupt occurs at the end of the address cycle the master is alway...

Page 768: ...interrupt at the end of the address cycle where an address match occurred interrupts resulting from subsequent data transfers have IAAS cleared A data transfer can now be initiated by writing informat...

Page 769: ...ignal Read Data from I2DR And Store Set TXAK 1 Generate STOP Signal 2nd Last Byte to be Last Byte to be Arbitration Lost Clear IAL IAAS 1 IAAS 1 SRW 1 Tx Rx Set TX Mode Write Data to I2DR Set RX Mode...

Page 770: ...I2 C Interface 32 16 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 771: ...es a single message digest or hash or integrity check value of all the data presented on the input bus using the MD5 or SHA 1 algorithms for bulk data hashing The MDHA includes these distinctive featu...

Page 772: ...ivate key presumably is only known by the sender This provides a measure of authentication and non repudiation A conceptual block diagram of the MDHA module is shown in Figure 33 1 Multiple input bloc...

Page 773: ...2 4 33 8 0xEC08_0010 MDHA Interrupt Status Registers MDISR 32 R 0x0000_0000 33 2 5 33 9 0xEC08_0014 MDHA Interrupt Mask Registers MDIMR 32 R W 0x0000_0000 33 2 5 33 9 0xEC08_001C MDHA Data Size Regist...

Page 774: ...authentication code full Allows the user to input a key and message data and have the accelerator do the complete MAC in one step Used directly with HMAC or EHMAC mode 0 Do not perform MAC FULL 1 Perf...

Page 775: ...lgorithm SHA 1 1 Message Digest 5 MD5 Table 33 3 Invalid MDMR Bit Settings MDMR bit settings Comments Setting any reserved bits IPAD 1 OPAD 1 Asserting both of the signals at the same time causes a mo...

Page 776: ...trol Register MDCR Table 33 4 MDCR Field Descriptions Field Description 31 21 Reserved should be cleared 20 16 DMAL DMA request level Represents the minimum number of words available in the FIFO betwe...

Page 777: ...ription 31 4 Reserved should be cleared 3 GO Go Indicates that all data has been loaded into the input FIFO and the module should complete all processing This bit is self clearing 0 Do not complete al...

Page 778: ...te of the autopadder for debug purposes 000 Perform standard auto padding 001 Pad last word 010 Add a word for padding 011 Last hash for the EHMAC 100 Stall state Auto Padder passes no data to engine...

Page 779: ...1 Error has occurred 1 DONE Done interrupt Read only Indicates that the MDHA module has completed processing the requested amount of data 0 Not complete 1 Done processing 0 INT MDHA single interrupt R...

Page 780: ...the data size written to the MDDSR is greater then the amount of data written to the FIFO 0 No error 1 Datasize is greater than the message size 8 ERE Early read error Read only A context register wa...

Page 781: ...gisters 0 MDx0 The MDHA message digest registers 0 consist of five 32 bit registers MDA0 MDB0 MDC0 MDD0 and MDE0 These registers store the five SHA 1 or four MD5 32 bit longwords that are the final an...

Page 782: ...d any attempts to read from them always returns the value zero Address 0xEC08_0030 MDA0 0xEC08_0034 MDB0 0xEC08_0038 MDC0 0xEC08_003C MDD0 0xEC08_0040 MDE0 Reset 0x0123_4567 Reset 0x89AB_CDEF Reset 0x...

Page 783: ...generates a single interrupt to the interrupt controller 33 3 2 FIFO The FIFO block contains a 16 32 bit FIFO that is used for temporary storage of the data to be hashed 33 3 3 MDHA Logic The MDHA lo...

Page 784: ...elerator that is capable of computing the Secure Hash Algorithm SHA 1 or Message Digest 5 MD5 33 3 3 5 Hashing Engine Control This module is the control unit of the MDHA that is capable of computing t...

Page 785: ...nterrupts optional DMA and set the DMA request level 3 MDMR register write Select algorithm data padding and algorithm initialization 4 MDDSR register write Load this register with the length of the m...

Page 786: ...done interrupt is triggered then read the message digest and the message digest count from the message digest registers 33 4 3 2 Generation of Key with OPAD 1 Reset the MDHA using the MDCMR SWR bit 2...

Page 787: ...ponse if it is waiting for message data This most likely occurs if the MDDSR write is not received or auto padding is disabled and a partial message block is provided 13 If MDSR DONE is set or done in...

Page 788: ...algorithm data padding HMAC or EHMAC and MACFULL bits 4 Direct context load of key into MDx1 registers 5 MDMDS register write Load this register with the length of the key 6 Fill data FIFO with messag...

Page 789: ...ize for NMAC load with data size of 0 bytes 9 Fill data FIFO with message to be hashed 10 MDHA does the required algorithm s auto padding of the message 11 Set the MDCMR GO bit 12 Wait for MDSR INT to...

Page 790: ...Message Digest Hardware Accelerator MDHA 33 20 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 791: ...ate random data CAUTION There is no known cryptographic proof showing that this is a secure method of generating random data In fact there may be an attack against the random number generator if its o...

Page 792: ...0000_0000 34 2 1 34 2 0xEC08_8004 RNG Status Register RNGSR 32 R 0x0010_0000 34 2 2 34 3 0xEC08_8008 RNG Entropy Register RNGER 32 W 0x0000_0000 34 2 3 34 4 0xEC08_800C RNG Output FIFO RNGOUT 32 R 0x0...

Page 793: ...0 0 Figure 34 2 RNG Status Register RNGSR Table 34 3 RNGSR Field Descriptions Field Description 31 24 Reserved must be cleared 23 16 OFS Output FIFO size Indicates size of the output FIFO 16 words and...

Page 794: ...d to monitor how many 32 bit words are currently resident in the FIFO A new random word pushes into the FIFO every 256 clock cycles as long as the FIFO is not full It is very important to poll RNGSR O...

Page 795: ...Logic Block This block contains the RNG s control logic as well as its core engine that generates random data 34 3 2 1 RNG Control Block The control block contains the address decoder all addressable...

Page 796: ...urned on 34 4 Initialization Application Information The intended general operation of the RNG is as follows 1 Reset initialize 2 Write to the RNG entropy register optional 3 Write to the RNG control...

Page 797: ...key with parity ECB CBC and CTR modes Triple DES 3DES 2 key 3 key 128 bits 192 bits with parity Key parity check ECB CBC and CTR modes 35 1 1 1 Data Ecryption Standard DES 3DES Algorithm The SKHA is a...

Page 798: ...e recovered Figure 35 1 DES Encryption Process In addition the SKHA module can compute 3DES which is an extension to the DES algorithm whereby every 64 bit input block is processed three times The SKH...

Page 799: ...35 1 1 4 Cipher Block Chaining CBC Cipher Mode Cipher Block Chaining mode encrypts the output of the previous block with the current block input as shown in Figure 35 5 For decryption the previous ci...

Page 800: ...ock processed The modulus size can be set between 28 through 2128 by powers of 8 SKMR CTRM The running counter is encrypted and XOR d with the plaintext to derive the ciphertext or with the ciphertext...

Page 801: ...4 SKHA Error Status Mask Register SKEMR 32 R W 0x0000_0000 35 2 5 35 10 0xEC08_4018 SKHA Key Size Register SKKSR 32 R W 0x0000_0000 35 2 6 35 12 0xEC08_401C SKHA Data Size Register SKDSR 32 R W 0x0000...

Page 802: ...Context 3 SKC3 32 R W 0x0000_0000 35 2 11 35 14 0xEC08_407C SKHA Context 4 SKC4 32 R W 0x0000_0000 35 2 11 35 14 0xEC08_4080 SKHA Context 5 SKC5 32 R W 0x0000_0000 35 2 11 35 14 0xEC08_4084 SKHA Conte...

Page 803: ...y parity errors 1 Do not check for DES key parity errors Note A mode error is generated if this bit is set to one while in AES mode 7 5 Reserved should be cleared 4 3 CM Cipher mode Selects the cipher...

Page 804: ...ould be cleared 21 16 IDMAL Input DMA Request Level Indicates the minimum number of words available in the input FIFO between DMA requests This value must be 32 words or less 000001 100000 1 32 words...

Page 805: ...alizes memory and clears all registers except SKHA Error Status Mask and Control registers This bit is self clearing 0 No Reinitialization 1 Reinitialize SKHA module 0 SWR Software Reset Functionally...

Page 806: ...size registers may not be modified and context registers may not be read while busy 0 SKHA idle 1 SKHA busy 3 RD Reset done Indicates if reset of the SKHA module has completed 0 Reset in progress 1 R...

Page 807: ...level 0 No error 1 Invalid DMA request level 10 KRE Key read error An illegal attempt to read the key registers during processing has been detected 0 No error 1 Key read error occurred 9 KPE Key parit...

Page 808: ...the message The SKDSR may be read at any time to determine the number of bytes that remain to be processed This value may be modified during message processing The value written is internally added to...

Page 809: ...generated and SKESR OFU is set The SKSR OFL field described in Section 35 2 4 SKHA Status Register SKSR can be polled to monitor how many 32 bit words are currently resident in the FIFO 35 2 10 SKHA K...

Page 810: ...lower bytes in the lowest 32 bit context register Example 35 1 Context Loading 0x0123456789ABCDEF101112131415161718191A1B1C1D1E1F would be loaded as follows SKC1 0x000102030405060708090A0B0C0D0E0F SKC...

Page 811: ...s of seven functional blocks The input FIFO the output FIFO transmit FIFO interface receive FIFO interface internal bus interface top control and the SKHA logic AES ECB AES CBC IV1 DES CTR Counter1 AE...

Page 812: ...that the host has loaded all the message data 35 3 2 Receive FIFO Interface Block This block translates the internal FIFO control signals to the output FIFO and pass the processed message data from t...

Page 813: ...sters SKESR SKESMR and an interrupt is triggered to the interrupt controller If an error occurs the SKHA core engine is halted This prevents the core from continuing operation with invalid data These...

Page 814: ...ol logic in turn returns a done signal to the SKHA logic block along with the processed message block When the entire message is processed following write to the End of Message register the SKHA logic...

Page 815: ...ead contents of context registers if necessary 13 Set the SKCMR CI bit to clear the done interrupt 35 4 2 Operation with DMA The intended DMA operation of the SKHA is as follows for ECB CBC and CTR mo...

Page 816: ...the SKCMR GO bit 9 Wait for done interrupt SKSR DONE 10 Unload processed message data from the output FIFO 11 Read context registers and store contents in memory 12 Set the SKCMR CI bit to clear the...

Page 817: ...variety of commands can be sent to the processor to access memory registers and peripherals The external emulator uses a three pin serial full duplex channel See Section 36 4 1 Background Debug Mode B...

Page 818: ...dress attribute register BAAR BKPT configurable interrupt CSR BKD Level 1 and level 2 triggers on OR condition in addition to AND SYNC_PC command to display the processor s current PC B 1001 3 new PC...

Page 819: ...contain a 5 bit field DRc that specifies the register as shown in Table 36 3 Processor Status Clock PSTCLK Delayed version of the processor clock Its rising edge appears in the center of valid PST and...

Page 820: ...3 Debug Module Memory Map DRc 4 0 Register Name Width bits Access Reset Value Section Page 0x00 Configuration status register CSR 32 R W See Note 0x0098_0000 36 3 2 36 5 0x05 BDM address attribute reg...

Page 821: ...contains status information from the breakpoint logic CSR is write only from the programming model It can be read from and written to through the BDM port CSR is accessible in supervisor mode as debu...

Page 822: ...l of debug module functionality An emulator could use this information to identify the level of functionality supported 0000 Revision A 0001 Revision B 0010 Revision C 0011 Revision D 1001 Revision B...

Page 823: ...n of Taken Branch PST 0x5 7 Reserved must be cleared 6 NPL Non pipelined mode Determines whether the core operates in pipelined mode or not 0 Pipelined mode 1 Non pipelined mode The processor effectiv...

Page 824: ...gnal to the on chip peripherals The debug mode output is logically defined as Debug mode output CSR FDBG CSR DBGH and Core is halted 0 Debug mode output is not forced asserted 1 Debug mode output core...

Page 825: ...ster AATR DRc 4 0 0x06 AATR Access Supervisor write only BDM write only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W RM SZM TTM TMM R SZ TT TM Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 Figure 36 4 Address At...

Page 826: ...ruction and through the BDM port using the WDMREG command 4 3 TT Transfer Type Compared with the local bus transfer type signals 00 Normal processor access 01 Reserved 10 Emulator mode access 11 Reser...

Page 827: ...the breakpoint trigger 0 Disables all level 2 breakpoints 1 Enables all level 2 breakpoint triggers 28 22 L2ED Enable Level 2 Data Breakpoint Setting an L2ED bit enables the corresponding data breakpo...

Page 828: ...ger PC_condition Address_range Data_condition Note Debug Rev A only had the AND condition available for the triggers 14 L1T Level 1 Trigger Determines the logic operation for the trigger between the P...

Page 829: ...n 1 Invert data breakpoint comparators 4 2 L1EA Enable Level 1 Address Breakpoint Setting an L1EA bit enables the corresponding address breakpoint Clearing all three bits disables the address breakpoi...

Page 830: ...1 10 9 8 7 6 5 4 3 2 1 0 R W Address Reset Figure 36 6 PC Breakpoint Register PBR0 Table 36 9 PBR0 Field Descriptions Field Description 31 0 Address PC Breakpoint Address The address to be compared wi...

Page 831: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Mask Reset Figure 36 8 PC Breakpoint Mask Register PBMR Table 36 11 PBMR Field Descriptions Field Description 31 0 Mask PC Breakpoint Mask 0 The corresponding PBR...

Page 832: ...9 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W Data Reset Figure 36 10 Data Breakpoint Registers DBR Table 36 14 DBR Field Descriptions Field Description 31 0 Data Data Breakpoint Value Contains...

Page 833: ...e control of the processor and thus the system This feature allows quick hardware debugging with the same tool set used for firmware development 36 4 1 1 CPU Halt Although most BDM operations can occu...

Page 834: ...d the GO command causes the processor to exit halted state and pass control to the instruction address in the PC bypassing normal reset exception processing If the PC was not loaded the GO command cau...

Page 835: ...fer The development system must count clock cycles in a given transfer C0 C4 are described as C0 Set the state of the DSI bit C1 First synchronization cycle for DSI DSCLK is high C2 Second synchroniza...

Page 836: ...clock periods 15 0 Data Data Contains the message to be sent from the debug module to the development system The response message is always a single word with the data field encoded as shown above 16...

Page 837: ...module the bottom half indicates the debug module s response to the previous development system commands Command and result transactions overlap to minimize latency Table 36 19 BDM Field Descriptions...

Page 838: ...al transfers that begin during a memory access return a not ready response Results are returned in the two serial transfer cycles after the memory access completes For any command performing a byte si...

Page 839: ...ddress Steal 36 4 1 5 4 36 26 0x1800 byte 0x1840 word 0x1880 lword Dump memory block DUMP Used with READ to dump large blocks of memory An initial READ executes to set up the starting address of the b...

Page 840: ...bit result A bus error response is returned if the CPU core is not halted Command Result Formats Command Sequence Figure 36 18 RAREG RDREG Command Sequence Operand Data None Result Data The contents...

Page 841: ...ddress bits to 0s for word and longword accesses to ensure that word addresses are word aligned and longword addresses are longword aligned Command Result Formats 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 842: ...Memory Location WRITE Write data to the memory location specified by the longword address BAAR TT TM defines address space Hardware forces low order address bits to 0s for word and longword accesses t...

Page 843: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 0x1 0x8 0x0 0x0 A 31 16 A 15 0 X X X X X X X X D 7 0 Word 0x1 0x8 0x4 0x0 A 31 16 A 15 0 D 15 0 Longword 0x1 0x8 0x8 0x0 A 31 16 A 15 0 D 31 16 D 15 0 Figure...

Page 844: ...READ is executed to set up the starting address of the block and to retrieve the first result If an initial READ is not executed before the first DUMP an illegal command response is returned The DUMP...

Page 845: ...and Result Formats Command Sequence Figure 36 26 DUMP Command Sequence Operand Data None 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte Command 0x1 0xD 0x0 0x0 Result X X X X X X X X D 7 0 Word Command 0x...

Page 846: ...Subsequent FILL commands use this address perform the write increment it by the current operand size and store the updated address in the temporary register If an initial WRITE is not executed precedi...

Page 847: ...egins at the current address in the PC and at the current privilege level If any register such as the PC or SR is altered by a BDM command while the processor is halted the updated value is used when...

Page 848: ...the next PC with the address being captured in the DDATA logic under control of the CSR BTB bits The specific sequence of PST and DDATA values is defined below 1 Debug signals a SYNC_PC command is pen...

Page 849: ...cial bus cycle to access the specified control register The 12 bit Rc field is the same the processor s MOVEC instruction uses Command Result Formats Command Sequence Figure 36 36 RCREG Command Sequen...

Page 850: ...e of the processor if SR S 1 then A7 Supervisor Stack Pointer OTHER_A7 User Stack Pointer else A7 User Stack Pointer OTHER_A7 Supervisor Stack Pointer Table 36 21 Control Register Map Rc Register Defi...

Page 851: ...sr restore the original macsr Likewise to write an accumulator register the following BDM sequence is needed BdmWriteACCx rcreg macsr read current macsr contents and save wcreg 0 macsr disable all rou...

Page 852: ...ister RDMREG Read the selected debug module register and return the 32 bit result The only valid register selection for the RDMREG command is CSR Command Result Formats Table 36 22 shows the definitio...

Page 853: ...e CPU accesses are performed using the WDEBUG instruction Command Format Table 36 3 shows the definition of the DRc write encoding Command Sequence Figure 36 42 WDMREG Command Sequence Operand Data Lo...

Page 854: ...d processor status operands or branch addresses The breakpoint status is also posted in the CSR CSR BSTAT is cleared by a CSR read when a level 2 breakpoint is triggered or a level 1 breakpoint is tri...

Page 855: ...exits emulator mode After the debug interrupt handler completes execution the external development system can use BDM commands to read the reserved memory locations In revision B B the hardware inhibi...

Page 856: ...TDR should be disabled while breakpoint registers are loaded after which TDR can be written to define the exact trigger This prevents spurious breakpoint triggers Because there are no hardware interlo...

Page 857: ...he first processor clock cycle of an instruction s execution Certain change of flow opcodes plus the PULSE and WDDATA instructions generate different encodings 0x2 Used by the debug translate module t...

Page 858: ...the DDATA pins Encodings 0x9 0xB identify the number of bytes displayed 3 The new target address is optionally available on subsequent cycles using the DDATA port The number of bytes of displayed on...

Page 859: ...ing speed of 240 MHz the ColdFire debug interface on PST DDATA must run slower to support emulator technology This is accomplished with the debug translate block which effectively time shifts the PST...

Page 860: ...ster In this definition the y suffix generally denotes the source and x denotes the destination operand For a given instruction the optional operand data is displayed only for those effective addresse...

Page 861: ...a y Dx PST 0x1 PST 0x9 DD source operand divu l ea y Dx PST 0x1 PST 0xB DD source operand divu w ea y Dx PST 0x1 PST 0x9 DD source operand eor l Dy ea x PST 0x1 PST 0xB DD source PST 0xB DD destinatio...

Page 862: ...e operand or l Dy ea x PST 0x1 PST 0xB DD source PST 0xB DD destination ori l data Dx PST 0x1 pea l ea y PST 0x1 PST 0xB DD destination operand pulse PST 0x4 rems l ea y Dw Dx PST 0x1 PST 0xB DD sourc...

Page 863: ...and 4 are never captured nor displayed because these accesses are treated as instruction fetches For all types of exception processing the PST 0xC value is driven at all times unless the PST output is...

Page 864: ...xt23 Rx PST 0x1 move l ACCy ACCx PST 0x1 move l ACCy Rx PST 0x1 move l MACSR CCR PST 0x1 move l MACSR Rx PST 0x1 move l MASK Rx PST 0x1 msac l Ry Rx ACCx PST 0x1 msac l Ry Rx ea y Rw ACCx PST 0x1 PST...

Page 865: ...n Berg connector arranged 2 x 13 as shown below Figure 36 45 Recommended BDM Connector rte PST 0x7 PST 0xB DD source operand PST 0x3 PST 0x B DD source operand PST 0x5 PST 0x9AB DD target address stop...

Page 866: ...Debug Module 36 50 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 867: ...s from the board edge connector through the standard four pin test access port TAP and the JTAG reset pin TRST 37 1 1 Block Diagram Figure 37 1 shows the block diagram of the JTAG module Figure 37 1 J...

Page 868: ...ation refer to Section 36 4 1 Background Debug Mode BDM JTAG_EN 0 37 2 External Signal Description The JTAG module has five input and one output external signals as described in Table 37 1 37 2 1 JTAG...

Page 869: ...The TMS pin is the test mode select input that sequences the TAP state machine TMS is sampled on the rising edge of TCLK The TMS pin has an internal pull up resistor The BKPT pin is used to request an...

Page 870: ...DSO pin provides serial output data in BDM mode 37 3 Memory Map Register Definition The JTAG module registers are not memory mapped and are only accessible through the TDO DSO pin 37 3 1 Instruction...

Page 871: ...the update DR state The DSE bit selects the drive strength used in JTAG mode IR 4 0 0_0001 IDCODE Access User read only 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 872: ...f a TAP controller state machine which is responsible for generating all control signals that execute the JTAG instructions and read write data registers 37 4 2 TAP Controller The TAP controller is a...

Page 873: ...LE PRELOAD 00010 Selects boundary scan register for shifting sampling and preloading without disturbing functional operation SAMPLE 00011 Selects boundary scan register for shifting and sampling witho...

Page 874: ...data The update DR state and the falling edge of TCLK can then transfer this data to the update cells The data is applied to the external output pins by the EXTEST or CLAMP instruction 37 4 3 3 SAMPLE...

Page 875: ...ing HIGHZ turns off all output drivers including the 2 state drivers and selects the bypass register HIGHZ also asserts internal reset for the MCU system logic to force a predictable internal state 37...

Page 876: ...Leaving the test logic reset state negates the ability to achieve low power but does not otherwise affect device functionality The TCLK input is not blocked in low power stop mode To consume minimal...

Page 877: ...ionally this mapping is selected because it easily maps into the ColdFire access control registers which provide a coarse association between memory addresses and their attributes e g cacheable non ca...

Page 878: ...ntroller IACK 0xFC05_8000 22 I2 C Table A 13 0xFC05_C000 23 QSPI Table A 14 0xFC06_0000 24 UART0 Table A 15 0xFC06_4000 25 UART1 0xFC06_8000 26 UART2 0xFC07_0000 28 DMA Timer 0 Table A 16 0xFC07_4000...

Page 879: ...Register 1 D1 32 R W 0x0000_0670 No 3 2 1 3 6 Load 0x082 7 Store 0x182 7 Data Register 2 7 D2 D7 32 R W Undefined No 3 2 1 3 6 Load 0x088 8E Store 0x188 8E Address Register 0 6 A0 A6 32 R W Undefined...

Page 880: ...ster CSR 32 R W See Note 0x0098_0000 36 3 2 36 5 0x05 BDM address attribute register BAAR 321 1 Each debug register is accessed as a 32 bit register reserved fields are not used don t care W 0x05 36 3...

Page 881: ...cess Control Register E PACRE 32 R W 0x4444_4444 11 2 3 11 4 0xFC00_0044 Peripheral Access Control Register F PACRF 32 R W 0x4444_4444 11 2 3 11 4 0xFC00_0048 Peripheral Access Control Register G PACR...

Page 882: ...tion Page 0xFC00_8000 n 0xC Chip Select Address Register CSARn n 0 5 32 R W 0x0000_0000 17 3 1 17 4 0xFC00_8004 n 0xC Chip Select Mask Register CSMRn n 0 5 32 R W 0x0000_0000 17 3 2 17 5 0xFC00_8008 n...

Page 883: ...19 4 10 19 16 0xFC03_00C4 Transmit Control Register TCR 32 R W 0x0000_0000 19 4 11 19 17 0xFC03_00E4 Physical Address Low Register PALR 32 R W Undefined 19 4 12 19 18 0xFC03_00E8 Physical Address High...

Page 884: ...8 W 0x00 16 6 12 16 14 0xFC04_4026 eDMA Interrupt Request Register EDMA_INT 32 R W 0x0000 16 6 13 16 15 0xFC04_402E eDMA Error Register EDMA_ERR 32 R W 0x0000 16 6 14 16 15 0xFC04_4100 hex n eDMA Chan...

Page 885: ...t Interrupt Mask SIMR1 8 W 0x00 14 2 5 14 8 0xFC04_C01D Clear Interrupt Mask CIMR1 8 W 0x00 14 2 6 14 9 0xFC04_C040 n n 1 63 Interrupt Control Registers ICR1n 8 R W 0x00 14 2 7 14 9 0xFC04_C0E0 Softwa...

Page 886: ...RT2 0xFC06_0000 0xFC06_4000 0xFC06_8000 UART Mode Registers1 UMR1n UMR2n 8 R W 0x00 31 3 1 31 5 31 3 2 31 6 0xFC06_0004 0xFC06_4004 0xFC06_8004 UART Status Register USRn 8 R 0x00 31 3 3 31 8 UART Cloc...

Page 887: ...transmission or reception of characters Register contents may also be changed Table A 16 DMA Timer Module Memory Map Address Register Width bits Access Reset Value Section Page DMA Timer 0 DMA Timer...

Page 888: ...dresses have no effect and result in a cycle termination transfer error 0xFC08_0000 0xFC08_4000 0xFC08_8000 0xFC08_C000 PIT Control and Status Register PCSRn 16 R W 0x0000 28 2 1 28 3 0xFC08_0002 0xFC...

Page 889: ...bits are reserved for expansion Write accesses to these reserved address spaces and reserved register bits have no effect 2 A 32 bit access to any of these registers results in a bus transfer error s...

Page 890: ...ddress locations have no effect and result in a bus error 0xFC0A_0004 Chip Configuration Register CCR 16 R See Section 9 3 1 9 3 0xFC0A_0008 Reset Configuration Register RCON 16 R 0x0001 9 3 2 9 4 0xF...

Page 891: ...o effect and result in a bus error 2 The MISCCR and CDR registers are described in Chapter 9 Chip Configuration Module CCM Table A 24 GPIO Module Memory Map Address Register Width bits Access Reset Va...

Page 892: ...0xFC0A_4025 PDDR_LCDCTLL 8 R W 0x00 13 3 2 13 17 Port Pin Data Set Data Registers 0xFC0A_4028 PPDSDR_FECH 8 R W See Section 13 3 3 13 19 0xFC0A_4029 PPDSDR_FECL 8 R W See Section 13 3 3 13 19 0xFC0A_...

Page 893: ...3 3 4 13 21 0xFC0A_404A PCLRR_LCDDATAM 8 W 0x00 13 3 4 13 21 0xFC0A_404B PCLRR_LCDDATAL 8 W 0x00 13 3 4 13 21 0xFC0A_404C PCLRR_LCDCTLH 8 W 0x00 13 3 4 13 21 0xFC0A_404D PCLRR_LCDCTLL 8 W 0x00 13 3 4...

Page 894: ...5 Table A 25 Real Time Clock Memory Map Address Register Width bits Access Reset Value Section Page 0xFC0A_8000 RTC Hours and Minutes Counter Register RTC_HOURMIN 32 R W Undefined 25 3 1 25 3 0xFC0A_8...

Page 895: ...Register LCD_PCCR 32 R W 0x0000_0000 22 3 12 22 16 0xFC0A_C030 LCD DMA Control Register LCD_DCR 32 R W 0x8010_0004 22 3 13 22 16 0xFC0A_C034 LCD Refresh Mode Control Register LCD_RMCR 32 R W 0x0000_0...

Page 896: ...6 21 16 Operational Registers 0xFC0B_0140 USB Command USBCMD Y H D 32 R W 0x0008_0000 21 3 3 1 21 17 0xFC0B_0144 USB Status USBSTS Y H D 32 R W 0x0000_0080 21 3 3 2 21 19 0xFC0B_0148 USB Interrupt Ena...

Page 897: ...xFC0B_4000 Identification Register ID N 32 R 0x0041_FA05 21 3 1 1 21 9 0xFC0B_4004 General Hardware Parameters HWGENERAL N 32 R 0x0000_02C5 21 3 1 2 21 10 0xFC0B_4008 Host Hardware Parameters HWHOST N...

Page 898: ...0x0000_0000 18 4 4 18 19 0xFC0B_8110 SDRAM Chip Select 0 Configuration SDCS0 32 R W 0x0000_0000 18 4 5 18 20 0xFC0B_8114 SDRAM Chip Select 1 Configuration SDCS1 32 R W 0x0000_0000 18 4 5 18 20 Table...

Page 899: ...r Width bits Access1 Reset Value Section Page 0xEC08_0000 MDHA Mode Register MDMR 32 R W 0x0000_0000 33 2 1 33 3 0xEC08_0004 MDHA Control Register MDCR 32 R W 0x0000_0000 33 2 2 33 6 0xEC08_0008 MDHA...

Page 900: ...8 SKHA Key Size Register SKKSR 32 R W 0x0000_0000 35 2 6 35 12 0xEC08_401C SKHA Data Size Register SKDSR 32 R W 0x0000_0000 35 2 7 35 12 0xEC08_4020 SKHA Input FIFO SKIN 32 R W 0x0000_0000 35 2 8 35 1...

Page 901: ..._0000 35 2 11 35 14 Table A 34 RNG Block Memory Map Address Register Width bits Access Reset Value Section Page 0xEC08_8000 RNG Control Register RNGCR 32 R W 0x0000_0000 34 2 1 34 2 0xEC08_8004 RNG St...

Page 902: ...Register Memory Map Quick Reference A 26 Freescale Semiconductor MCF5329 Reference Manual Rev 3...

Page 903: ...n Signal Information and Muxing table Core In the figure D0 Hardware Configuration Info updated information for bit 10 Changed reset values for VBR from 0x0000_0000 to undefined for the lower reserved...

Page 904: ...exBus Changed bit description for CSCRn RDAH WRAH fields Updated introduction sentence for figure Longword Read Burst from 8 Bit Port 3 1 1 1 Address Setup and Hold added note added footnote to AH and...

Page 905: ...OTG Changed USB_INTR NAKE ULPIE from read only to read write in register figure Changed ID reset value from 0x0041_FA05 to 0x0042_FA05 Corrected address offsets for the following registers CAPLENGTH f...

Page 906: ...d MSB to msb and LSB to lsb throughout RTC Changed reset value of RTC_DAYS from undefined to 0x0000_0000 Added plus one minute and note to RTC stopwatch register description Corrected RTC_CR SWR bit d...

Page 907: ...I O Table 2 1 Page 2 2 Change MCF5327 196 MAPBGA ball locations for the following signals Table 2 10 Page 2 13 Change LCD_SCLK to LCD_LSCLK to be consistent with the rest of the reference manual Tabl...

Page 908: ...pace Section 5 4 6 Page 5 14 Change first sentence from Ways 0 and 1 of the data cache can be locked by setting CACR DHLCK likewise ways 0 and 1 of the instruction cache can be locked by setting CACR...

Page 909: ...lowing signals Corrected DSCR_MISC field description table title Previously mislabeled as DSCR_I2C Interrupt Controller Marked CLMASK values 0x8 0xE as reserved in CLMASKfield description table Added...

Page 910: ...S table entry add the following note Note If a read is attempted from a DDR SDRAM chip select when there is no memory to respond with the appropriate SD_DQS pulses the bus cycle hangs Because there is...

Page 911: ...This should be the Descriptor Group Lower Address Register GALR Table 19 4 Page 19 8 Add RMON_R_DROP to the MIB counter memory map at address 0xFC03_0280 with a description of Count of frames not coun...

Page 912: ...als the maximum packet length and the total bytes is zero it waits for a zero length packet from the host to retire the current dTD Setting this bit disables the zero length packet When the device is...

Page 913: ...total FlexCAN interrupts added 16 individual interrupts per MB SSI Changed FIFO size from 8x24 to 8x32 Changed ACDAT from 19 bits to 20 bits wide from SSI_ACDAT 18 0 to SSI_ACDAT 19 0 Figure 24 15 Pag...

Page 914: ...ast 3 bits of register are 000 Clarified last sentence of first paragraph in memory map section regarding quiscent DSCLK during WDEBUG JTAG Added MCF53281 IDCODE values Figure 37 3 Page 37 4 Updated t...

Page 915: ...bit address tag to TAG 20 bit address tag Table 9 10 Page 9 10 Correct boot port size D 4 3 settings They should match Table 9 3 Table 11 1 Page 11 2 Change reset values of MPR0 to 0x7777_7777 Change...

Page 916: ...heable and one ACR is then used to identify cacheable addresses e g ADDR 31 0 identifies the cacheable space Table B 3 MCF5329RM Rev 0 1 to Rev 1 Changes continued Location Description Table 12 1 Cros...

Page 917: ...nge FEC functions to Reserved as the FEC signals are not available as alternate functions on the LCD pins Table 14 15 Page 14 12 Correct source 25 Flag clearing mechanism entry from Write CWIR CWIC 1...

Page 918: ...e ordering of the transfer buffers to match the host microprocessor bus architecture The bit fields in the register interface and the DMA data structures including the setup buffer within the device Q...

Page 919: ...crystal oscillator mode intended for factory test IRQ 7 1 x TA x Only when used as TA D0 x During reset only QSPI_DOUT x I2 C mode only I2C_SDA QSPI_CLK x I2 C mode only I2C_SCL FEC_MDIO x I2 C mode...

Page 920: ...pulse Indicates start of next frame O Line Pulse Horizontal Sync LCD_LP LCD_HSYNC Passive matrix Line pulse Active matrix Horizontal sync pulse Indicates start of next line O Shift Clock LCD_SCLK Clo...

Page 921: ...0x8000_0000 and 0x8000_8000 actually modify the exact same memory location System software should ensure that SRAM address pointers do not exceed the size of the SRAM to prevent unwanted overwriting o...

Page 922: ...5k pull up resistor on DP full speed operation or DN low speed operation ports to Device operation requires a 1 5k pull up resistor on DP full speed operation because low speed operation is not suppor...

Page 923: ...ule Universal Serial Bus Interface On The Go Module Liquid Crystal Display Controller LCDC FlexCAN Synchronous Serial Interface SSI Real Time Clock Pulse Width Modulation PWM Module Watchdog Timer Mod...

Page 924: ...nterface Host Module Universal Serial Bus Interface On The Go Module Liquid Crystal Display Controller LCDC FlexCAN Synchronous Serial Interface SSI Real Time Clock Pulse Width Modulation PWM Module W...

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