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ColdFire Core
3-2 Freescale Semiconductor
Figure 3-1. V3 ColdFire Core Pipelines
The instruction fetch pipeline (IFP) is a four-stage pipeline for prefetching instructions. The prefetched
instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the
instruction, fetches the required operands and then executes the required function. Because the IFP and
OEP pipelines are decoupled by an instruction buffer serving as a FIFO queue, the IFP is able to prefetch
instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for
instructions.
The V3 ColdFire core pipeline stages include the following:
• Four-stage instruction fetch pipeline (IFP) (plus optional instruction buffer stage)
— Instruction address generation (IAG) — Calculates the next prefetch address
— Instruction fetch cycle 1 (IC1) — Prefetch on the processor’s local bus
— Instruction fetch cycle 2 (IC2) — Completes prefetch on the processor’s local bus
— Instruction early decode (IED) — Generates time-critical decode signals needed for the OEP
— Instruction buffer (IB) — Optional buffer stage minimizes fetch latency effects using FIFO
queue
Instruction
Instruction
FIFO
Decode & Select,
Address
Instruction
Operand
Data[31:0]
Instruction
Fetch Cycle 2
Instruction
Pipeline
Execution
Fetch
Pipeline
IAG
IC1
IC2
IED
IB
DSOC
AGEX
Address [31:0]
Instruction Buffer
Address
Generation
Fetch Cycle 1
Early Decode
Generation,
Execute
Operand Fetch
MCF5329 Reference Manual, Rev 3