Freescale Semiconductor MCF5329, Reference Manual, Page: 281 / 924

Interrupt Controller Modules
Freescale Semiconductor 14-13
30 I
2
C I2SR[IIF] I
2
C Interrupt Write I2SR[IIF] = 0
31 QSPI QIR register QSPI interrupt Write 1 to appropriate QIR bit
32 DTIM0 DTER0 register Timer 0 interrupt Write 1 to appropriate DTER0 bit
33 DTIM1 DTER1 register Timer 1 interrupt Write 1 to appropriate DTER1 bit
34 DTIM2 DTER2 register Timer 2 interrupt Write 1 to appropriate DTER2 bit
35 DTIM3 DTER3 register Timer 3 interrupt Write 1 to appropriate DTER3 bit
36
FEC
EIR[TXF] Transmit frame interrupt Write EIR[TXF] = 1
37 EIR[TXB] Transmit buffer interrupt Write EIR[TXB] = 1
38 EIR[UN] Transmit FIFO underrun Write EIR[UN] = 1
39 EIR[RL] Collision retry limit Write EIR[RL] = 1
40 EIR[RXF] Receive frame interrupt Write EIR[RXF] = 1
41 EIR[RXB] Receive buffer interrupt Write EIR[RXB] = 1
42 EIR[MII] MII interrupt Write EIR[MII] = 1
43 EIR[LC] Late collision Write EIR[LC] = 1
44 EIR[HBERR] Heartbeat error Write EIR[HBERR] = 1
45 EIR[GRA] Graceful stop complete Write EIR[GRA] = 1
46 EIR[EBERR] Ethernet bus error Write EIR[EBERR] = 1
47 EIR[BABT] Babbling transmit error Write EIR[BABT] = 1
48 EIR[BABR] Babbling receive error Write EIR[BABR] = 1
49–61 Not Used
62 SCM SCMIR[CFEI] Core bus error interrupt Write SCMIR[CFEI] = 1
63 Not Used
Table 14-15. Interrupt Source Assignment For INTC0 (continued)
Source Module Flag Source Description Flag Clearing Mechanism
MCF5329 Reference Manual, Rev 3