Freescale Semiconductor MCF5329, Reference Manual, Page: 134 / 924

Cache
5-8 Freescale Semiconductor
Figure 5-6. Data Caching Operation
The following steps determine if a cache line for a given address is allocated:
1. The cache set index, A[11:4], selects one cache set.
2. A[31:12] and the cache set index are used as a tag reference or are used to update the cache line
tag field. A[31:12] can specify 20 possible addresses that can be mapped to one of the four ways.
3. The four tags from the selected cache set are compared with the tag reference. A cache hit occurs
if a tag matches the tag reference and the V bit is set, indicating that the cache line contain valid
data. If a cacheable write access hits in a valid cache line, the write can occur to the cache line
without having to load it from memory.
If the memory space is copyback, the updated cache line is marked modified (M = 1), because the
new data has made the data in memory out of date. If the memory location is write-through, the
write is passed on to system memory and the M bit is never used. The tag does not have TT or TM
bits.
To allocate a cache entry, the cache set index selects one of the cache’s 256 sets. The cache control logic
looks for an invalid cache line to use for the new entry. If none are available, the cache controller uses a
pseudo-round-robin replacement algorithm to choose the line to be deallocated and replaced. First the
cache controller looks for an invalid line, with way 0 the highest priority. If all lines have valid data, a 2-bit
replacement counter is used to choose the way. After a line is allocated, the pointer increments to point to
the next way.
0 3 4 11 12 31
Index Tag Data/Tag Reference
MUX
Comparator
0
1
2
3
Logical OR
Hit 3
Hit 2
Hit 1
Hit 0
Hit
Line Select
Set 0
Set 1
Set 255
•
•
•
Address
A[31:12]
Way 0
Way 1
Way 2
Way 3
TAG STATUS LW0 LW1 LW2 LW3
TAG STATUS LW0 LW1 LW2 LW3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Address
Set Select
A[11:4]
Data or
Instruction
MCF5329 Reference Manual, Rev 3