Freescale Semiconductor MCF5329, Reference Manual, Page: 384 / 924

SDRAM Controller (SDRAMC)
18-22 Freescale Semiconductor
Many commands require a delay before the next command may be issued; sometimes the delay depends
on the type of the next command. These delay requirements are managed by the values programmed in the
memory controller configuration registers (SDCFG1, SDCFG2).
18.5.1.1 Row and Bank Active Command (
ACTV
)
The
ACTV
command is responsible for latching the row and bank address and activating the specified row
bank of a memory block. After the row is activated, it can be accessed using subsequent read and write
commands.
NOTE
The SDRAMC supports one active row for each chip select block. See
Section 18.6.1, “Page Management,” for more information.
18.5.1.2 Read Command (
READ
)
When the SDRAMC receives a read request via the internal bus, it first checks the row and bank of the
new access. If the address falls within the active row of an active bank, it is a page hit, and the read is issued
as soon as possible (pending any delays required by previous commands). If the address is within an
inactive bank, the memory controller issues an ACTV followed by the read command. If the address is not
within the active row of an active bank, the memory controller issues a pre command to close the active
Table 18-12. SDRAM Commands
Function Symbol CKE CS RAS CAS WE BA[1:0] A[10] Other A
Command Inhibit
INH
H H X X X X X X
No Operation
NOP
H L H H H X X X
Row and Bank Active
ACTV
H L L H H V V V
Read
READ
H L H L H V L V
Write
WRITE
H L H L L V L V
Burst Terminate (SDR/DDR only)
BST
H L H H L X X X
Precharge All Banks
PALL
H L L H L X H X
Precharge Selected Bank
PRE
H L L H L V L X
Load Mode Register
LMR
H L L L L LL V V
Load Extended Mode Register
LEMR
H L L L L LH V V
Auto Refresh
REF
H L L L H X X X
Self Refresh
SREF
H
→
L L L L H X X X
Power Down
PDWN
H
→
L H X X X X X X
H = High
L = Low
V = Valid
X = Don’t care
MCF5329 Reference Manual, Rev 3