Figure 42-1. PWM Block Diagram
The PWM follows IP Bus protocol for interfacing with the processor core. It does not
interface with any other modules inside the device except for the clock and reset inputs
from the Clock Control Module (CCM) and interrupt signals to the processor interrupt
handler. The PWM includes a single external output signal, PMWO. The PWM includes
the following internal signals:
• Three clock inputs
• Four interrupt lines
• One hardware reset line
• Four low power and debug mode signals
• Four scan signals
• Standard IP slave bus signals
42.1.2 Clocks
The clock that feeds the prescaler can be selected from:
Introduction
i.MX 6Solo/6DualLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
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Freescale Semiconductor, Inc.
