In MII mode, there are 18 signals defined by the IEEE 802.3 standard and supported by
the EMAC. MII, RMII and RGMII modes uses a subset of the 18 signals. These signals
are listed in table below.
Table 37-1. Pin Usage in MII, RMII and RGMII Modes
Direction
EMAC Pin
Name
MII Usage
RMII Usage
RGMII Usage
In/Out
FEC_MDIO
Management Data Input/Output Management Data
Input/output
Management Data Input/Output
Out
FEC_MDC
Management Data Clock
General output
Management Data Clock
Out
FEC_TXD[0]
Data out, bit 0
Data out, bit 0
Data out, bit 0
Out
FEC_TXD[1]
Data out, bit 1
Data out, bit 1
Data out, bit 1
Out
FEC_TXD[2]
Data out, bit 2
Not Used
Data out, bit 2
Out
FEC_TXD[3]
Data out, bit 3
Not Used
Data out, bit 3
Out
FEC_TX_EN
Transmit Enable
Transmit Enable
Transmit Enable
Out
FEC_TX_ER
Transmit Error
Not Used
Not Used
In
FEC_CRS
Carrier Sense
Not Used
Not Used
In
FEC_COL
Collision
Not Used
Not Used
In
FEC_TX_CLK
Transmit Clock
Not Used
Synchronous clock reference (REF_CLK,
can connect from PHY)
In
FEC_RX_ER
Receive Error
Receive Error
Not Used
In
FEC_RX_CLK
Receive Clock
Not Used
Synchronous clock reference (REF_CLK,
can connect from PHY)
In
FEC_RX_DV
Receive Data Valid
Receive Data Valid
and generate CRS
RXDV XOR RXERR on the falling edge
of FEC_RX_CLK.
In
FEC_RXD[0]
Data in, bit 0
Data in, bit 0
Data in, bit 0
In
FEC_RXD[1]
Data in, bit 1
Data in, bit 1
Data in, bit 1
In
FEC_RXD[2]
Data in, bit 2
Not Used
Data in, bit 2
In
FEC_RXD[3]
Data in, bit 3
Not Used
Data in, bit 3
The MII management interface consists of two pins, FEC_MDIO, and FEC_MDC. The
FEC hardware operation can be divided in the parts listed below. For detailed information
consult the i.MX 6 Multimedia Applications Processor Reference Manual.
• Transmission-The Ethernet transmitter is designed to work with almost no
intervention from software. Once ECR[ETHER_EN] is asserted and data appears in
the transmit FIFO, the Ethernet MAC is able to transmit onto the network. When the
transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit logic
asserts FEC_TX_EN and starts transmitting the preamble (PA) sequence, the start
frame delimiter (SFD), and then the frame information from the FIFO. However, the
controller defers the transmission if the network is busy (FEC_CRS asserts).
Hardware Operation
i.MX 6Solo/6DualLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
272
Freescale Semiconductor, Inc.
