CONFIG_IMX_PCIE=y
CONFIG_IMX_PCIE_EP_MODE_IN_EP_RC_SYS=y
# CONFIG_IMX_PCIE_RC_MODE_IN_EP_RC_SYS is not set
36.5.3 Features
Set up the link between RC and EP by their stand-alone 125MHz running internally.
In the EP system, EP can access the reserved DDR memory (default address:
0x40000000) of the PCIe RC system by the interconnection between PCIe EP and PCIe
RC.
NOTE
• The layout of the 1G DDR memory on the SD board is
0x1000_0000-0x4FFF_FFFF). Use mem=768M in the
kernel command line to reserve the
0x4000_0000-0x4FFF_FFFF DDR memory space for the
EP access test.
• Boot up the PCIe EP system, and then boot up the PCIe RC
system.
• Example of the RC kernel command line:
noinitrd console=ttymxc0,115200,mem=768M root=/dev/nfs
nfsroot=<your_rootfs> ip=dhcp rw
36.5.4 Results
When the ARM core is used as the bus master (define EP_SELF_IO_TEST in pcie.c
driver):
Regarding to the log listed in the following table, the data size of each TLP when the
cache is enabled, is about 4 times of the data size in write, and 2 times of the data size in
read, when the cache is disabled.
ARM core used as the bus master,
and the cache is disabled
ARM core used as the bus master,
and the cache is enabled
Data size in one write TLP
8 bytes
32 bytes
Write speed
~109 MB/s
~298 MB/s
Data size in one read TLP
32 bytes
64 bytes
Read speed
~29 MB/s
~100 MB/s
When the cache is enabled:
Chapter 36 i.MX 6 PCI Express Root Complex Driver
i.MX 6Solo/6DualLite Linux Reference Manual, Rev. L3.0.35_4.1.0, 09/2013
Freescale Semiconductor, Inc.
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