2.3.2.6 DMA Controller
Data from the host computer is received automatically by the STB signal via the external Centronics
interface. The data is input to the input buffer on the DRAM (IC5). At this time, E05A96 detects the
rising edge of the external STB signal and outputs the STBDMA (strobe DMA request) signal to the
CPU. When the CPU detects this signal, the DMA controller in the CPU sends a bus request to the
bus controller in the CPU, and then the CPU releases the bus line. Due to this, external data is
transported into the memory, bypassing the CPU.
B A C
D M A C
BA R E Q
E05A96 (IC2)
S T B
STB DM A
CPU H8 (IC1)
A C K
B U S Y
DR E Q 1
9
1 2 9
D M A R Q
1 2 8
1 4
DR E Q 2
1 6 6
1 6 1
1 6 2
M emo ry
Figure 2-26. DMA Controller Operation
Operating Principles
Stylus Pro XL
2-22
REV.-A
Summary of Contents for Stylus Pro XL
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