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Dynamic Engineering PMC-BiSerial-III HW2, User Manual

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Dynamic Engineering PMC-BiSerial-III HW2 User Manual Download Page 38

 

 

              

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the CRC status to determine if the message is valid.  It is important that the host keep 
up with the hardware on an interrupt basis to make sure the CRC is checked for each 
message before the next packet is received.  Once set, the CRC stays set until 
explicitly cleared by the software.  If the CRC is bad, and the host does not keep up 
then more than one message will have to be considered bad.  The Manchester error 
and Post Amble error bits have the same restrictions.  The three bits are located in the 
same register and can be checked in one operation. 
 

Summary of Contents for PMC-BiSerial-III HW2

Page 1: ...8891 Fax 831 457 4793 www dyneng com sales dyneng com Est 1988 User Manual PMC BiSerial III HW2 32 channel Bi directional Manchester SDLC and Asynchronous Interface PMC Module Revision A Corresponding...

Page 2: ...d without notice Furthermore Dynamic Engineering assumes no liability arising out of the application or use of the device described herein The electronic equipment described herein generates uses and...

Page 3: ...19 BIS3_IO_DATA 20 BIS3_IO_DIR 20 BIS3_IO_TERM 21 BIS3_IO_MUX 21 BIS3_IO_UCNTL 22 BIS3_IO_RDBK 22 BIS3_IO_RDBKUPR 23 BIS3_STAT_FIFO 23 BIS3_PLL_CMD PLL_RDBK 24 BIS3_SM_CNTL7 0 25 BIS3_SDLC_CNTL5 0 28...

Page 4: ...O PIN ASSIGNMENT 44 APPLICATIONS GUIDE 45 Interfacing 45 CONSTRUCTION AND RELIABILITY 46 THERMAL CONSIDERATIONS 46 WARRANTY AND REPAIR 47 SERVICE POLICY 47 OUT OF WARRANTY REPAIRS 47 FOR SERVICE CONTA...

Page 5: ...C BISERIAL III DIRECTION CONTROL PORT 20 FIGURE 13 PMC BISERIAL III TERMINATION CONTROL PORT 21 FIGURE 14 PMC BISERIAL III MUX CONTROL PORT 21 FIGURE 15 PMC BISERIAL III UPPER CONTROL PORT 22 FIGURE 1...

Page 6: ...igured as either one full duplex SDLC I O or two full duplex asynchronous UART I O Other custom interfaces are available We will redesign the state machines and create a custom interface protocol That...

Page 7: ...n has 32 Dual Port RAM DPR blocks implemented using the Xilinx internal block RAM Each channel has one or more associated DPRs depending on which mode is active Each DPR is configured to have a 32 bit...

Page 8: ...s are divided into six four channel blocks that can each be configured as either one full duplex SDLC interface or two full duplex asynchronous interfaces The SDLC interface uses programmable PLL cloc...

Page 9: ...nchronous interfaces in a channel block are independently configurable and each have separate receive and transmit interrupts All the data I O lines on the HW2 are programmable to be register controll...

Page 10: ...software compatibility system prototyping may be done on one PMC Carrier board with final system implementation uses a different one The PMC BiSerial III uses a 10 mm inter board spacing for the front...

Page 11: ...wo additional clock periods account for the 1 clock delay to decode the signals from the PCI bus and to convert the terminate with data state into the TRDY signal The BiSerial III can support many pro...

Page 12: ...ol The Manchester and Post Amble errors are also latched in status bits This document is somewhat restricted as to the technical content allowed in describing the electrical interface The document Poi...

Page 13: ...interrupt line The remaining two interrupt lines are not used in SDLC mode An asynchronous interface is also available on the PMC BiSerial III HW2 This protocol uses one start bit low eight data bits...

Page 14: ...port BIS3_SM_CNTL_7 0x005C 23 Chan 7 state machine control read write port BIS3_SDLC_CNTL_0 0x0060 24 Chan 8 SDLC control read write port BIS3_ASYNC_CNTL_0 0x0060 24 Chan 8 asynchronous control read w...

Page 15: ...e port BIS3_SM_MEM_14 0x07800 Dual port RAM 14 read write port BIS3_SM_MEM_15 0x08000 Dual port RAM 15 read write port BIS3_SM_MEM_16 0x08800 Dual port RAM 16 read write port BIS3_SM_MEM_17 0x09000 Du...

Page 16: ...n be configured to respond to the channel interrupts on an individual basis After the interrupt is received the data can be retrieved An efficient loop can then be implemented to fetch the data New me...

Page 17: ...be individually enabled and used for status without driving the backplane Polled operation can be performed in this mode Interrupt Set When 1 and the Master is enabled this bit forces an interrupt re...

Page 18: ...made See the programming section for the current FLASH revision BIS3_START_SET BIS3_START_RDBK 08 BiSerial III Start Set Control Register Port read write Start Set Register DATA BIT DESCRIPTION 7 0 Ch...

Page 19: ...he active channels The state machine may be running at a significantly slower rate than the PCI bus There may be some delay in sensing that the start abort has been set for a particular channel The de...

Page 20: ...onto the corresponding parallel port lines This port is direct read write of the register The I O side is read back from the BIS3_IO_RDBK port It is possible that the output data does not match the I...

Page 21: ...with that bit is closed to create a parallel termination of approximately 100 In most systems the receiving side is terminated and the transmitting side is not The drivers can handle termination on bo...

Page 22: ...ata Data transmitted when the Mux is set to 0 and the direction is set to 1 Termination when set to 1 causes the parallel termination to be engaged Setting the Mux control bits to 0 creates a parallel...

Page 23: ...ransceivers from the external I O The upper bits are presented on this port BIS3_STAT_FIFO 24 BiSerial III Switch Port read only User Switch Port DATA BIT DESCRIPTION 31 24 Spare 23 16 sw7 0 15 0 Spar...

Page 24: ...fferent state than the written SDAT bit To read back the contents of the CMD port use the RDBK port PLL Enable When this bit is set to a one SDAT is enabled When set to 0 SDAT is tri stated by the Xil...

Page 25: ...ndicates operation at the high speed 5 MHz nominal In Low speed mode 0 the system operates at 400 Khz Bi_Uni when set 1 indicates that bidirectional operation is requested When cleared 0 unidirectiona...

Page 26: ...errupt is set for each packet received In either case the interrupt is generated by the state machine and captured by the interrupt holding register By reading BIS3_INT_STAT the interrupt source s can...

Page 27: ...d The Manchester error is set when an illegal Manchester encoding happens when properly coded data is expected For example if a message is programmed to be of one length and a shorter length is receiv...

Page 28: ...d Receive Enable When this bit is a one the receiver is enabled to receive data and store it in the dual port RAM starting with the address stored in the receiver start address register if it is the f...

Page 29: ...nsmitter start address register When this bit is a zero no action is taken Load Transmit End Address When this bit is a one the value in the address input field is loaded into the transmitter end addr...

Page 30: ...receiver is enabled to receive characters and store them in the dual port RAM starting with the address stored in the receiver start address register if it is the first message since the receiver was...

Page 31: ...ster When this bit is a zero no action is taken Load Transmit End Address When this bit is a one the value in the address input field is loaded into the transmitter end address register When this bit...

Page 32: ...7 4 mode 10 1 0 Channel 3 0 mode 10 FIGURE 23 PMC BISERIAL III CHANNEL MODE CONTROL REGISTER The first two channel blocks channels 0 7 are hard wired to HW1 mode The remaining six channel blocks can...

Page 33: ...D4 BiSerial III I20 Address Register I2O Address Register DATA BIT DESCRIPTION 31 0 Address FIGURE 25 PMC BISERIAL III I2O ADDRESS REGISTER The physical address where the I2O interrupt status should b...

Page 34: ...for receive data The first 256 locations are used for TX and the upper 256 for receive in BiDirectional mode In Unidirectional Mode the memory is all allocated to either RX or TX and starts at offset...

Page 35: ...request will be generated Each packet can have a different setting for this bit Once at the end of message interrupt on every packet alternate packets etc At the end of the packet the hardware can app...

Page 36: ...d of Message is also set to address 0x0D control register for channel so this would be a 1 packet case The CRC is calculated by a slightly non standard process The CRC is calculated on the message not...

Page 37: ...cting the proper speed of operation The receiver will look for a valid pre amble before accepting data When a valid pre amble is found the data is captured and stored into the DPR The CRC is calculate...

Page 38: ...ecked for each message before the next packet is received Once set the CRC stays set until explicitly cleared by the software If the CRC is bad and the host does not keep up then more than one message...

Page 39: ...nt 0 Transmit Interrupt Transmit 0 Interrupt Channel 0 Interrupt Int 1 Receive Interrupt Receive 0 Interrupt Channel 1 Interrupt Int 2 unused Transmit 1 Interrupt Channel 2 Interrupt Int 3 unused Rece...

Page 40: ...d until that bit in the status register is explicitly cleared When an interrupt occurs the Master interrupt enable should be cleared and the status register read to determine the cause of the interrup...

Page 41: ...external cable with the following pins connected SIGNAL Ch 0 1 1 35 2 36 Ch 2 3 3 37 4 38 Ch 4 5 5 39 6 40 Ch 6 7 7 41 8 42 Ch 8 9 9 43 10 44 Ch 10 11 11 45 12 46 Ch 12 13 13 47 14 48 Ch 14 15 15 49 1...

Page 42: ...ation and not needed by this design 12V unused 1 2 GND INTA 3 4 5 6 BUSMODE1 5V 7 8 9 10 GND 11 12 CLK GND 13 14 GND 15 16 5V 17 18 AD31 19 20 AD28 AD27 21 22 AD25 GND 23 24 GND C BE3 25 26 AD22 AD21...

Page 43: ...gned by the specification and not needed by this design 12V unused 1 2 3 4 GND 5 6 GND 7 8 9 10 11 12 RST BUSMODE3 13 14 BUSMODE4 15 16 GND 17 18 AD30 AD29 19 20 GND AD26 21 22 AD24 23 24 IDSEL AD23 2...

Page 44: ..._5m 6 40 IO_6p IO_6m 7 41 IO_7p IO_7m 8 42 IO_8p IO_8m 9 43 IO_9p IO_9m 10 44 IO_10p IO_10m 11 45 IO_11p IO_11m 12 46 IO_12p IO_12m 13 47 IO_13p IO_13m 14 48 IO_14p IO_14m 15 49 IO_15p IO_15m 16 50 IO...

Page 45: ...I when it is not powered can damage it as well as the rest of the host system This problem may be avoided by turning all power supplies on and off at the same time Alternatively the use of OPTO 22 iso...

Page 46: ...insertion easy and reliable The PMC is secured against the carrier with four screws attached to the 2 stand offs and 2 locations on the front panel The four screws provide significant protection again...

Page 47: ...mpany the return Dynamic Engineering will not be responsible for damages due to improper packaging of returned items For service on Dynamic Engineering Products not purchased directly from Dynamic Eng...

Page 48: ...Options Tristate or transmit IDLE pattern between messages append post amble pattern calculate and append CRC in hardware interrupt on a packet basis RX Data rates accepted Continuous at 5 MHz or 400...

Page 49: ...Embedded Solutions Page 49 of 50 Temperature Coefficient 2 17 W oC for uniform heat across PMC Power Max TBD mA 5V Temperature range 0 70 standard Extended Temperature available 40 85...

Page 50: ...W2 Driver software and user application Data sheet reprints are available from the manufacturer s web site Note The Engineering Kit is strongly recommended for first time PMC BiSerial III purchases Sc...

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