Embedded Solutions
Page 34 of 50
BIS3_SM_MEM31-0
[$0x800 – 0x10000] BiSerial III HW2 Dual Port RAM address space
The following discussion applies to the HW1 operating mode only. In SDLC or
asynchronous mode the DPRs are used to store I/O data only and each DPR is always
used as either a receive buffer or a transmit buffer, but never both.
Each channel has Dual Port RAM (DPR) associated with it. The DPR is configured to
have a 32-bit port on the PCI side and a 16-bit port on the I/O side. Each DPR is 1K x
16 on the I/O side and 512 x 32 on the PCI side.
When using BiDirectional mode the memory is further divided with an upper half and a
lower half. The lower half is used for transmit and the upper half for receive data. The
first 256 locations are used for TX and the upper 256 for receive in BiDirectional mode.
In Unidirectional Mode the memory is all allocated to either RX or TX, and starts at
offset 0x00.
The DPR is used to store the packet or packets of data to be transmitted or that have
been received. When transmitting the data should be loaded prior to starting. It is
possible to load additional data while transmitting if the software has tight control over
the system timing.
In transmit the first 32 bits are the control word. The packet follows: Label, length, data,
CRC. The CRC will normally be Set to 0x00 and the hardware instructed to create and
insert the CRC.
Location I/O Value
0 lower
command
1 upper
command
2 label
3 length
4 First
data
…
N last
data
N+1 CRC or zero data
Location PCI
0
upper lower command
1 length
label
2
data 1 data 0
…
N
CRC data last or data last data last –1
XXXX CRC
