Dynamic Engineering PMC-BiSerial-III HW2, User Manual

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Embedded Solutions
Page 32 of 50
BIS3_CHAN_MODE
[$C8] BiSerial III HW2 Channel Mode Control Register
Channel Mode Control Register
DATA BIT DESCRIPTION
31-16 Spare
15-14 Channel 31-28 mode (bit 15 = ‘0’)
13-12 Channel 27-24 mode (bit 13 = ‘0’)
11-10 Channel 23-20 mode (bit 11 = ‘0’)
9-8 Channel 19-16 mode (bit 9 = ‘0’)
7-6 Channel 15-12 mode (bit 7 = ‘0’)
5-4 Channel 11-8 mode (bit 5 = ‘0’)
3-2 Channel 7-4 mode = “10”
1-0 Channel 3-0 mode = “10”
FIGURE 23 PMC BISERIAL-III CHANNEL MODE CONTROL REGISTER
The first two channel blocks (channels 0 - 7) are “hard-wired” to HW1 mode. The
remaining six channel blocks can each be configured to be one full-duplex SDLC
channel using four I/O lines and four DPR blocks (2 each for transmit and receive) or
two full-duplex asynchronous channels each using two I/O lines and two DPR blocks (1
each for transmit and receive).
The mode definitions for each channel block are as follows:
One SDLC channel
= “00”
Two ASYNC channels = “01”
Four HW1 channels = “10”