Embedded Solutions
Page 25 of 50
BIS3_SM_CNTL7-0
[$5C, 58, 54, 50, 4C, 48, 44, 40] BiSerial III HW2 Control Registers (Active when mode = “10”)
State Machine Control Registers
DATA BIT
DESCRIPTION
31 Ready_Busy
(read
only)
30
Manchester Error Status / CLR
29-20
Address Pointer (read only)
19
Post Amble Status / CLR
18
CRC Error Status / CLR
17-8
End of Message
5
INTEN
4 CLREN
3 Bi_Uni
2
IDLE Pattern Transmit
1
HI_LOW Speed
0 TX/RX
Operation
FIGURE 20
PMC BISERIAL-III STATE MACHINE CONTROL REGISTERS
Each state-machine has a separate control register to govern the operation of the
channel. In addition, the TX channels have control via the data in the Dual Port RAM
associated with that channel.
TX/RX when set ‘1’ indicates transmit operation. When cleared ‘0’ indicates receiver
operation.
HI_LOW when set ‘1’ indicates operation at the “high speed” = 5 MHz nominal. In Low
speed mode ‘0’ the system operates at 400 Khz.
Bi_Uni when set ‘1’ indicates that bidirectional operation is requested. When cleared
‘0’ unidirectional operation is selected. In Bidirectional operation the memory is set to
operate with the lower half allocated to TX and the upper half to RX. The counter will
roll over to the correct boundaries (end of memory to 1/2, and 1/2 – 1 to start or end of
memory to start) based on the mode of operation. Continuous operation is possible.
In BiDirectional mode the transmitter is only enabled when transmitting. When the
transmission is completed the hardware automatically clears the TX bit and restarts in
RX mode (BiDir only) without clearing the start bit. This allows a response, and wait for
data without software intervention.
In Unidirectional mode the transmitter is enabled whenever there is data to send or the
idle pattern is sent (if enabled). The transmitter will send as many packets as the
