Embedded Solutions
Page 29 of 50
Receive Interrupt Enable : When this bit is a one the receiver interrupt is enabled.
The interrupt will occur at the end of a message transmission, which is determined by
the detection of a SDLC flag character (0x7e) after the message has started. When
this bit is a zero the interrupt status will still be latched, but will not cause an interrupt to
occur. The receive interrupt is mapped to the second interrupt line in its channel block;
the remaining two interrupt lines are not used in SDLC mode.
Load Receive Start Address : When this bit is a one the value in the address input
field is loaded into the receiver start-address register. When this bit is a zero no action
is taken.
Load Transmit Start Address : When this bit is a one the value in the address input
field is loaded into the transmitter start-address register. When this bit is a zero no
action is taken.
Load Transmit End Address : When this bit is a one the value in the address input
field is loaded into the transmitter end-address register. When this bit is a zero no
action is taken.
Address Input : This field is used with the three load address bits to specify address
boundaries for the transmit and receive state machines.
Send an Abort : When this bit is set to a one the transmit state-machine will send an
abort character (0xfe) provided a transmission is currently in progress. When this bit is
a zero normal operation will continue.
Receive End Address : This field represents the address that the last received data
word is stored in. Note that this is a 16-bit address, bit 0 indicates which half of the
appropriate long-word the last 16-bit word was stored (0 -> lower half, 1 -> upper half).
Abort Detected : When an abort character is detected by the receiver, this status bit
will be latched and can be cleared by writing a one back in this bit position.
