Embedded Solutions
Page 11 of 50
Theory of Operation
The PMC BiSerial-III-HW2 is designed for transferring data from one point to another
with three simple serial protocols.
The PMC BiSerial-III-HW2 features a Xilinx FPGA. The FPGA contains all of the
registers and protocol controlling elements of the BiSerial III design. Only the PLL,
transceivers, and switches are external to the Xilinx device.
The PMC BiSerial-III is a part of the PMC Module family of modular I/O products. It
meets the PMC and CMC draft Standards. In standard configuration, the PMC
BiSerial-III is a Type 1 mechanical with only low-profile components on the back of the
board and one slot wide, with 10 mm inter-board height. Contact Dynamic Engineering
for a copy of this specification. It is assumed that the reader is at least casually familiar
with this document and basic logic design.
The PCI interface to the host CPU is controlled by a logic block within the Xilinx. The
BiSerial III design requires one wait state for read or write cycles to any address. The
PMC BiSerial-III is capable of supporting 40 MBytes per second into and out of the
DPR. With a Windows® read/write loop better than 20 MB/sec is attained on most
computers. The wait states refer to the number of clocks after the PCI core decode
before the “terminate with data” state is reached. Two additional clock periods account
for the 1 clock delay to decode the signals from the PCI bus and to convert the
terminate with data state into the TRDY signal.
The BiSerial III can support many protocols. The PMC BiSerial-III-HW2 uses
Manchester serial encoded data and clock for its point-to-point interface. Data is sent
in 16-bit words; concatenated for multiple word transfers. The Manchester timing is
shown in the next diagram.
State machines within the FPGA control all transfers to and from the internal RAM and
I/O logic. The TX state machine reads from the transmit memory and loads the shift
registers before sending the data. The RX state machine receives data from the data
buffers and takes care of moving data from the shift register into the RX memory.
Data is read from the TX memory. The first two locations are control words. The
control words are stored for state-machine use. The first data word is then read and
loaded into the output shift register and the CRC generator. The Shift register is
enabled to shift the data out. As the bits are shifted out of the shift register the data is
encoded for Manchester compatibility. When the last data word has been loaded into
the CRC and shift register, the hardware completes the CRC processing to be prepared
for the last load to the shift register. Once the CRC has been transmitted the hardware
checks to see if more data is to be sent or if this was the last packet in the message.
There are several options including using a software CRC instead of the hardware
