Embedded Solutions
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BIS3_INT_STAT
[$CC] BiSerial III Interrupt Status and Clear Register
Interrupt Status and Clear Register
DATA BIT
DESCRIPTION
31-0
Channel Interrupt or Clear bit
FIGURE 24
PMC BISERIAL-III INTERRUPT STATUS REGISTER
Each bit is set when an interrupt occurs on the associated channel. Each bit can be
cleared by writing to the register with the same bit position set (‘1’). You do not need to
rewrite with a ‘0’ – the clearing action happens during the write.
This register is in parallel with the I2O interrupts. Usually only one or the other will be in
use at a time. Both can be used if desired. Interrupt conditions are captured and
processed in both places.
BIS3_I2OAR
[$D4] BiSerial III I20 Address Register
I2O Address Register
DATA BIT
DESCRIPTION
31-0 Address
FIGURE 25
PMC BISERIAL-III I2O ADDRESS REGISTER
The physical address where the I2O interrupt status should be written to is stored in this
register. When active interrupts are detected the I2O sequence is started. The PCI bus
is requested, the hardware waits for the grant and then writes the captured status to the
stored address. Please note that this is the direct hardware address, and not an
indirect (translated) address.
The active bits are auto cleared and the process re-enabled for new active interrupts.
Interrupts that occur during an I2O cycle are stored until the hardware is re-enabled and
cause a second immediate processing cycle. The receiving hardware must be able to
handle multiple interrupt status writes in close succession. A FIFO is ideal for the
receiving hardware implementation.
