Embedded Solutions
Page 26 of 50
hardware is programmed to send, and at the end of the message clear the start bit.
The hardware will remain in transmit or receive mode until changed by software.
IDLE when ‘1’ and in transmit mode commands the state-machine to insert the idle
pattern when not sending data from the Dual Port RAM. In receive or BiDirectional
mode this bit should be set to zero.. When in transmit mode, and this bit is cleared the
transmitter is tri-stated between messages sent.
CLREN when set, and in transmit mode allows the start bit to be cleared at the end of a
message sent. Note that the start bit is not cleared until the last packet of the message
is sent. For Rx this bit has no effect.
Please note that in BiDirectional mode this bit should be set and the packet and end of
message addresses should be the same to cause a single packet to be sent and the TX
bit to be reset.
INTEN when set in RX or TX mode allows the channel to create an interrupt request.
The INTEN signal is applied after the holding register and before the interrupt request
to the PCI bus.
In TX mode there is a control bit in the DPR command that controls the interrupt to the
packet level. In RX mode the interrupt is set for each packet received. In either case
the interrupt is generated by the state machine, and captured by the interrupt holding
register. By reading BIS3_INT_STAT the interrupt source(s) can be checked.
If INTEN is not set then the Interrupt status register can be used to poll for status. With
individual INTEN bits each channel can be operated in polled or interrupt driven modes.
To use the interrupt method the master interrupt enable must also be enabled.
End of Message is the address to test the address pointer against for the end of
message. A message is a group of packets. The packet length is embedded in the
message. Please refer to the Memory section for more details on the packet length
control. As each packet is sent the hardware tests the end of message address to
determine if there are more packets to send.
The end of packet address includes the command word through the CRC. Starting with
‘0’ at the lower command word, and counting n 16 bit data words plus the CRC plus 1 =
the end of packet address. When the end of message address matches the end of
packet address the hardware recognizes that the last packet processing should occur.
The command word is 32 bits and takes 2 locations. The offset (for post increment),
label, length, and CRC take 1 each for a total of 6 –1 = 5 (count from zero) plus the
data length. For a message with 8 locations the end of packet address would be “D”.
