Embedded Solutions
Page 30 of 50
BIS3_ASYNC_CNTL11-0
[$B8, B0, A8, A0, 98, 90, 88, 80, 78, 70, 68, 60] BiSerial III HW2 Asynchronous Control
Registers (Active when mode = “01”)
Asynchronous Control Registers
DATA BIT
DESCRIPTION
30 Framing
Error/Clear
29-19
Receive End Address (read only)
18-9
Address Input
8
Clock Select
7
Load Transmit End Address
6
Load Transmit Start Address
5
Load Receive Start Address
4 Receive
Interrupt
Enable
3 Transmit
Interrupt
Enable
2 Transmit
Clear
Enable
1
Receive Enable
0 Transmit
Enable
FIGURE 22
PMC BISERIAL-III SDLC CONTROL REGISTERS
Transmit Enable : When this bit is a one the transmitter is enabled to send characters
starting with the address stored in the transmitter start-address register and continuing
until the data in the transmitter end-address register has been sent. When this bit is a
zero the transmitter is disabled.
Receive Enable : When this bit is a one the receiver is enabled to receive characters
and store them in the dual-port RAM starting with the address stored in the receiver
start-address register if it is the first message since the receiver was enabled, or in the
next 16-bit address after the end-address of the last message if it is not. When this bit
is a zero the receiver is disabled.
Transmit Clear Enable : When this bit is a one the transmit enable bit will be cleared
when the transmitted message completes. When this bit is a zero the transmitter will
remain enabled, but no more data will be sent unless a new end address is loaded.
Transmit Interrupt Enable : When this bit is a one the transmitter interrupt is enabled.
The interrupt will occur at when the transmit state-machine reaches the end address
stored in the transmitter end address register. When this bit is a zero the interrupt
status will still be latched, but will not cause an interrupt to occur. The transmit interrupt
is mapped to the first or third interrupt line in its channel block depending on whether it
is the first or second asynchronous interface in that block.
