Embedded Solutions
Page 19 of 50
BIS3_START_CLR
[$0C] BiSerial III Start Clear Control Register Port write only
Start Clear Register
DATA BIT
DESCRIPTION
7-0
Clear the active Start Bits
FIGURE 10
PMC BISERIAL-III START CLEAR REGISTER
Writing a ‘1’ to a channel clear bit will cause that channels Start Bit to be cleared. The
Channel will complete the current operation and then abort processing. Reading from
the RDBK register will show the active channels. The state-machine may be running at
a significantly slower rate than the PCI bus. There may be some delay in sensing that
the start abort has been set for a particular channel.
The delay can be estimated to be the period of the clock in use and 12 periods. For
transmit the clock rate is 2x the data rate. For receive the clock rate is 8x the data rate.
At low speed in transmit mode the delay would be 12x (1/800 Khz) => 15 uS or so.
These are worst case delays.
Please note that the “ready_busy” bit can be used to check when an aborted channel is
ready for a new start command. Please refer to the channel control registers.
