Dallas DS87C550, User Manual Supplement

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DS87C550 High-Speed Microcontroller User’s Guide Supplement
90 of 93
As a simple example of this timing information, assume that the processor is in its reset default condition
running from an 11.0592 MHz crystal (or external clock), and the user wants to establish the maximum
repetition rate for PWM0 while maintaining a machine cycle clock of divide by 4. In this case,
X 2 / X 4 =
xx, CD1:0 = 10b, PW01S2:0 = 000b, and PW0FG = 00000000b. Since N = 00h (i.e., PW0FG = 00h), the
equation shows this combination will provide the maximum PWM clock rate. Performing the calculation:
PWM Clock =
1 N
4 / Osc
+
=
1 0
/4 MHz 11.0592
+
= 2.76 MHz
Since the PWM Pulse Generator section is basically an 8-bit counter (in 8-bit PWM mode), 256 clocks
are required for the counter to make one complete cycle. This dictates that the repetition rate of the PWM
channel will be the PWM clock/256. Therefore in this example, the repetition rate of PWM0 will be:
Repetition Rate (8-bit mode) =
256
Clock PWM
=
256
MHz 2.76
= 10.80 kHz
∴
92.59 us
PULSE GENERATOR
The Pulse Generator portion of the PWM function generates the PWM output. The logical operation of
the Pulse Generator section of PWM0 in 8-bit mode is illustrated in Figure PWM3. All other PWM
channels operate in a similar fashion. From the user’s perspective, the Pulse Generator can be considered
simply an 8-bit up counter driven by the PWM Clock. As this 8-bit counter rolls over from 0FFh to 00h,
the corresponding PWM output is set high. As the counter continues to count up and pass through the
user selected value stored in register PWM0, PWM1, PWM2, or PWM3, the PWM output is cleared to
zero. In this way, the duty cycle of the PWM output is determined by the value loaded by the user into the
PWMx (i.e., PWM0, PWM1, PWM2, PWM3) registers. The duty cycle of the PWM function is given by
the following equation:
PWM Duty Cycle(%) =
256
PWMx
With the minimum value of zero loaded into PWM register, the equation illustrates that this produces a
0% duty cycle signal (never goes high). With the maximum value of 255 loaded into the PWM register, a
duty cycle of 99.609% is generated. If a duty-cycle of precisely 100% is required, the DC override bits
PW0DC (PW01CON.6), PW1DC (PW01CON.2), PW2DC (PW23CON.6), and PW3DC (PW23CON.2)
will force the PWM output to be high for the entire cycle when set.