DS87C550 High-Speed Microcontroller User’s Guide Supplement
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SECTION 8: RESET CONDITIONS
The reset conditions of the DS87C550 are generally described in the High-Speed Microcontroller User’s
Guide and specific reset default conditions of the SFR bits may be found in the data sheet. However two
features have been added to the DS87C550. These new features are discussed below.
Oscillator Fail Detect Reset
Most members of the High-Speed Microcontroller family contain a watchdog timer. The intent of this
timer is to force the processor into a known “good” state (reset) if it ever entered a runaway situation
where it was not executing code properly. This is very powerful feature, but could be made stronger with
a simple addition. Since the watchdog timer clock was derived from the main crystal oscillator, it was
possible (though very unlikely) that the oscillator would fail (stop) leaving the processor in an undesirable
state. Since the watchdog timer runs from the same clock, the timer would stop counting which prevented
a time-out and a resulting reset. This possibility is eliminated in the DS87C550 by the inclusion of an
oscillator fail detection circuit. When enabled, this circuit causes the processor to be reset if the oscillator
frequency falls below TBD kHz. This puts the processor into a known good state regardless of the
watchdog timer if the main crystal oscillator should ever fail. Although the oscillator has failed when this
reset occurs, the processor is clocked into the normal reset state by other internal clocks.
The oscillator fail detect feature is enabled by setting the OFDE (PCON.4) bit with software. This bit can
be modified at any time. When an oscillator fail detection occurs, the flag OFDF (PCON.5) bit is set by
hardware when the processor enters reset. This bit must be cleared by software.
RST Pin as an Output
The DS87C550 is the first member of Dallas’ High-Speed Microcontroller family to make the reset pin
(RST) both an input and an output. Normally, this pin is an active high input for a reset signal generated
elsewhere in the system. With the DS87C550, this pin functions as an input as before, but now will also
provide an output when the reset originates from within the processor.
The possible internal sources of reset from the DS87C550 are:
1.
Power–on/Power-Fail reset
2.
Watchdog Timer reset
3.
Oscillator Fail reset
The reset output pulse duration is a function of the internal source of the reset. The worst case (minimum
pulse duration) occurs when the reset source is the watchdog timer whose reset cycle may be a single
machine-cycle long. When the watchdog timer creates a reset, the RST pin is set at the beginning of the
next machine cycle, and will remain active for one full machine cycle. When the internal source of the
reset is the power-fail circuit, the RST pin will be set at the beginning of the next machine cycle after the
reset trip point, and will remain as long as power will sustain it. When power returns, the RST pin will be
held active while the processor is held in power-up reset (65565 clocks). If the internal source of reset is
the oscillator fail detection circuit, the RST pin will be driven active asynchronously immediately after
the detection, and will be held there as long as the processor is in a reset state (presumably until the
oscillator begins operation again).
Since the RST pin is designed so that it can be overdriven by an LS-TTL gate output, it is important to
keep this pin lightly loaded (resistance and capacitance). For best results, a single buffer should be
connected to the RST pin when it used as an output for a system-wide reset signal. Under no
