Dallas DS87C550, User Manual Supplement

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DS87C550 High-Speed Microcontroller User’s Guide Supplement
57 of 93
Capture Trigger Control Register (CTCON)
7 6 5 4 3 2 1 0
SFR EBh
3 CT
CT3
2 CT
CT2
1 CT
CT1
0 CT
CT0
RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
3 CT
Bit 7
Capture Register CPTR3 Negative Trigger Enable. Setting this bit enables
the transfer of Timer 2 contents into 16-bit capture register pair CPTH3:CPTL3
on the falling edge of the signal on pin INT5/CT3 (P1.3). When set, this bit also
configures External Interrupt 5 to respond to a negative edge (if enabled).
Clearing this bit disables both capture and interrupt functions for a falling edge.
CT3
Bit 6
Capture Register CPTR3 Positive Trigger Enable. Setting this bit enables the
transfer of Timer 2 contents into 16-bit capture register pair CPTH3:CPTL3 on
the rising edge of the signal on pin INT5/CT3 (P1.3). When set, this bit also
configures External Interrupt 5 to respond to a positive edge (if enabled).
Clearing this bit disables both capture and interrupt functions for a rising edge.
2 CT
Bit 5
Capture Register CPTR2 Negative Trigger Enable. Setting this bit enables
the transfer of Timer 2 contents into 16-bit capture register pair CPTH2:CPTL2
on the falling edge of the signal on pin INT4/CT2 (P1.2). When set, this bit also
configures External Interrupt 4 to respond to a negative edge (if enabled).
Clearing this bit disables both capture and interrupt functions for a falling edge.
CT2
Bit 4
Capture Register CPTR2 Positive Trigger Enable. Setting this bit enables the
transfer of Timer 2 contents into 16-bit capture register pair CPTH2:CPTL2 on
the rising edge of the signal on pin INT4/CT2 (P1.2). When set, this bit also
configures External Interrupt 4 to respond to a negative edge (if enabled).
Clearing this bit disables both capture and interrupt functions for a rising edge.
1 CT
Bit 3
Capture Register CPTR1 Negative Trigger Enable. Setting this bit enables
the transfer of Timer 2 contents into 16-bit capture register pair CPTH1:CPTL1
on the falling edge of the signal on pin INT3/CT1 (P1.1). When set, this bit also
configures External Interrupt 3 to respond to a negative edge (if enabled).
Clearing this bit disables both capture and interrupt functions for a falling edge.
CT1
Bit 2
Capture Register CPTR1 Positive Trigger Enable. Setting this bit enables the
transfer of Timer 2 contents into 16-bit capture register pair CPTH1:CPTL1 on
the falling edge of the signal on pin INT3/CT1 (P1.1). When set, this bit also
configures External Interrupt 3 to respond to a positive edge (if enabled).
Clearing this bit disables both capture and interrupt functions for a rising edge.