DS87C550 High-Speed Microcontroller User’s Guide Supplement
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SECTION 5:CPU TIMING
The majority of the information contained in the original “High-Speed Microcontroller User’s Guide”
applies to the DS87C550. The only differences are found in the clock divider circuits between the crystal
oscillator (or external clock source) and the clock distribution circuitry. Early members of the High-Speed
Microcontroller family offer the option of 4, 256, or 1024 clocks per machine cycle. The DS87C550 can
operate at 1, 2, 4, or 1024 clocks per machine cycle. These selectable clock frequencies not only affect the
CPU’s frequency of operation (machine cycle clock), but also provide selectable clocks to the on-board
timers and other peripherals (system clock). It is important to note the difference in these clocks, as they
are sometimes confused, creating errors in timing calculations. The effects of these variable clocks
relative to CPU timing are discussed below. Their effect on peripheral timing can be found in the
individual peripherals’ sections of this document.
Crystal Selection
Some recent introductions to the High-Speed Microcontroller family contain special circuitry to allow
more latitude in crystal selection. It is frequently the case that as crystals go up in frequency, they become
more expensive, and less likely to be available in fundamental mode. While a fundamental mode, parallel
resonant, AT cut crystal is still required for these new family members, a simple clock multiplier has been
included to allow selection of more readily available crystals when high frequency operation is required.
An illustration of the clock multiplier function specifically and overall system clock generation and
control is shown in Figure 5-1.
SYSTEM CLOCK GENERATION AND CONTROL :
Figure 5-1
FREQUENCY
MULTIPLIER
CTM
(ENABLE)
4X/2X
from
CRYSTAL
OSCILLATOR
OR
EXRTERNAL
CLOCK SOURCE
DIVIDE
BY 256
CPU
STATE
CLOCK
GENERATION
(divide by 4)
CD1,CD0
SYSTEM
CLOCK
MACHINE CYCLE
CLOCK
00
10
11
MUX
As shown in the figure, the output of the crystal oscillator is provided directly to three blocks of circuitry:
the frequency multiplier, a divide by 256 block, and a 3-to-1 multiplexer. The frequency multiplier
function is enabled by setting the CTM bit, and produces outputs of Input-times-2 or Input-times-4 as
determined by the 4X/
X
2
bit. The multiplied clock is then passed to the multiplexer (MUX) that selects
the system clock source, and then to the CPU State Clock Generator. This clock multiplication feature
allows peak performance of the processor but with the use of a slower, often more available and less
expensive crystal. As an example, recall that the maximum frequency of the DS87C550 is 33 MHz. With
this clock multiplier feature, a crystal value of 8.25 MHz (33/4) can be used when the frequency
multiplier set to Input-times-4 mode. Alternatively with a crystal value of 16.5 MHz, it is possible to
recognize peak processor performance when the frequency multiplier is set to input-times 2 mode.
Recognize that regardless of the clock multiplication function, there is a maximum operational frequency
of the processor given in the specifications as “Oscillator Frequency”. Care must be taken not to violate
this specification when using the clock multiplier as unpredictable behavior of the processor can result.
