DS87C550 High-Speed Microcontroller User’s Guide Supplement
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The system clock or some derivative there of is provided to all of the peripherals inside the
microcontroller and the machine cycle clock provides the basic 4-state clock for all CPU functions. The
relationship of the crystal (or external oscillator) to the system clock and machine cycle clock along with
the control settings is shown in Table 5-1.
SYSTEM CLOCK CONTROL:
Table 5-1.
4X/
X
2
CD1:0
System
Clock
Machine Cycle
Clock
1
00
F
OSC
* 4
F
OSC
0
00
F
OSC
* 2
F
OSC
/2
x
01 (Reserved)
x
10
F
OSC
F
OSC
/ 4
x
11
F
OSC
/ 256
F
OSC
/ 1024
The case of CD1:0 = 11 is a special case for power savings, and is described in the section on power
management.
Changing System Clock Frequency
The microcontroller incorporates a special locking sequence to ensure “glitch-free” switching of the
internal clock signals. All changes to the CD1, CD0 bits must pass through the 10 (divide-by-four) state.
For example, to change from 00 (frequency multiplier) to 11 (PMM), the software must change the bits in
the following sequence: 00
10
11. Attempts to switch between invalid states will fail, leaving the
CD1, CD0 bits unchanged.
The following sequence must be followed when switching to the frequency multiplier as the internal time
source. This sequence can only be performed when the device is in divide-by-four operation. The steps
must be followed in this order, although it is possible to have other instructions between them. Any
deviation from this order will cause the CD1, CD0 bits to remain unchanged. Switching from frequency
multiplier to non-multiplier mode requires no steps other than the changing of the CD1, CD0 bits.
1.
Ensure that the CD1, CD0 bits are set to 10, and the RGMD (EXIF.2) bit = 0.
2.
Clear the CTM (Crystal Multiplier Enable) bit.
3.
Set the
2X
4X/
bit to the appropriate state.
4.
Set the CTM (Crystal Multiplier Enable) bit.
5.
Poll the CKRDY bit (EXIF.4), waiting until it is set to 1.
6.
Set CD1, CD0 to 00. The frequency multiplier will be engaged on the machine cycle following the
write to these bits.
