DS87C550 High-Speed Microcontroller User’s Guide Supplement
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Compare Register Two LSB (CMPL2)
7
6
5
4
3
2
1
0
SFR ABh
CMPL2.7
CMPL2.6
CMPL2.5
CMPL2.4
CMPL2.3
CMPL2.2
CMPL2.1
CMPL2.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
CMPL2.7-0
Bits 7-0
Compare Register Two LSB.
This register is one of three used to store the least
significant 8-bit value for the Timer 2’s comparison functions. When a match
occurs between Timer 2 and the contents of 16-bit register pair made of CMPH2
& CMPL2, port pin P4.6 will toggle if the corresponding compare match toggle
enable bit CMTE0 (RSTR.6) is set. Similarly on a match, P4.7 will toggle if the
corresponding compare match toggle enable bit CMTE1 (RSTR.7) is set.
Capture Register Zero LSB (CPTL0)
7
6
5
4
3
2
1
0
SFR ACh
CPTL0.7
CPTL0.6
CPTL0.5
CPTL0.4
CPTL0.3
CPTL0.2
CPTL0.1
CPTL0.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
CPTL0.7-0
Bits 7-0
Capture Register Zero LSB.
This register is used to capture the least significant
8-bit value for the Timer 2’s channel 0 capture function. When a transition
occurs on the INT2/CT0 pin, the LSB of Timer 2 is captured in this register on
the rising edge if the CT0=CTCON.0 enable bit is set or on the falling edge if the
0
CT
=CTCON.1 enable is set. Setting both enable bits will cause a capture to
occur on both edges.
Capture Register One LSB (CPTL1)
7
6
5
4
3
2
1
0
SFR ADh
CPTL1.7
CPTL1.6
CPTL1.5
CPTL1.4
CPTL1.3
CPTL1.2
CPTL1.1
CPTL1.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
CPTL1.7-0
Bits 7-0
Capture Register One LSB.
This register is used to capture the least significant
8-bit value for the Timer 2’s channel 1 capture function. When a transition
occurs on the INT3/CT1 pin, the LSB of Timer 2 is captured in this register on
the rising edge if the CT1=CTCON.1 enable bit is set or on the falling edge if the
1
CT
=CTCON.3 enable is set. Setting both enable bits will cause a capture to
occur on both edges.
