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Dallas DS87C550, User Manual Supplement

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Dallas DS87C550 User Manual Supplement Download Page 48

DS87C550 High-Speed Microcontroller User’s Guide Supplement

48 of 93

PWM0 Value Register (PWM0)

7

6

5

4

3

2

1

0

SFR DCh PWM0.7

PWM0.6

PWM0.5

PWM0.4

PWM0.3

PWM0.2

PWM0.1

PWM0.0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset

PWM0.7-0

Bits 7-0

PWM0 Value Register.  

This register provides read/write access to timer and

compare resources found in the pulse generator section of 8-bit PWM channel 0.
When bit PW0T/C (PW01CON.4) is 1, this register provides access to the timer
portion. Access to the timer allows precise initialization of the PWM function if
desired. When bit PW0T/C is 0, this register provides access to the compare
register that determines the duty cycle of channel 0’s output.  The duty cycle is
given by the equation Duty-Cycle (%) = PWM0/256. In 16-bit mode, this register
is the LSB value register for 16-bit PWM channel 0, and functions identically to
8-bit mode.

PWM1 Value Register (PWM1)

7

6

5

4

3

2

1

0

SFR DDh PWM1.7

PWM1.6

PWM1.5

PWM1.4

PWM1.3

PWM1.2

PWM1.1

PWM1.0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

RW-0

R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset

PWM1.7-0

Bits 7-0

PWM1 Value Register.  

This register provides read/write access to timer and

compare resources found in the pulse generator section of 8-bit PWM channel 1.
When bit PW1T/C (PW01CON.0) is 1, this register provides access to the timer
portion. Access to the timer allows precise initialization of the PWM function if
desired. When bit PW1T/C is 0, this register provides access to the compare
register that determines the duty cycle of channel 1’s output.  The duty cycle is
given by the equation Duty-Cycle (%) = PWM0/256. In 16-bit mode, this register
is the MSB value register for 16-bit PWM channel 0, and functions identically to
8-bit mode.

Summary of Contents for DS87C550

Page 1: ...Information on new members of the High Speed Microcontroller family has been added Section 3 Architecture No Changes Information containing new architectural features is contained in the DS87C550 data...

Page 2: ...are listed Section 14 Real Time Clock No changes Section 15 Battery Backup No changes Section 16 Instruction Set Details No changes Section 17 Troubleshoooting No changes Section 18 Analog to Digital...

Page 3: ...are planned to be made available Refer to individual data sheet for available versions DS87C550 QCL SPEED D 18 MHz G 25 MHz L 33 MHz R 40 MHz S 50 MHz TEMPERATURE C 0 C to 70 C PACKAGE M DIP Q PLCC E...

Page 4: ...DS87C550 High Speed Microcontroller User s Guide Supplement 4 of 93 SECTION 3 ARCHITECTURE No changes...

Page 5: ...2M T1M T0M MD2 MD1 MD0 8Eh P1 P1 7 TXD1 P1 6 RXD1 P1 5 T2EX P1 4 T2 P1 3 INT5 CT3 P1 2 INT4 CT2 P1 1 INT3 CT1 P1 0 INT2 CT0 90h RCON CKRDY RGMD RGSL BGS 91h SCON0 SM0 FE_0 SM1_0 SM2_0 REN_0 TB8_0 RB8_...

Page 6: ...ACC E0h PW01CS PW0S2 PW0S1 PW0S0 PW0EN PW1S2 PW1S1 PW1S0 PW1EN E1h PW23CS PW2S2 PW2S1 PW2S0 PW2EN PW3S2 PW3S1 PW3S0 PW3EN E2h PW01CON PW0F PW0DC PW0OE PW0T C PW1F PW1DC PW1OE PW1T C E3h PW23CON PW2F P...

Page 7: ...MR 1 0 0 0 0 0 0 0 9Fh P2 1 1 1 1 1 1 1 1 A0 SADDR0 0 0 0 0 0 0 0 0 A1h SADDR1 0 0 0 0 0 0 0 0 A2h IE 0 0 0 0 0 0 0 0 A8h CMPL0 0 0 0 0 0 0 0 0 A9h CMPL1 0 0 0 0 0 0 0 0 AAh CMPL2 0 0 0 0 0 0 0 0 ABh...

Page 8: ...D9h PWM0 0 0 0 0 0 0 0 0 DCh PWM1 0 0 0 0 0 0 0 0 DDh PWM2 0 0 0 0 0 0 0 0 DEh PWM3 0 0 0 0 0 0 0 0 DFh ACC 0 0 0 0 0 0 0 0 E0h PW01CS 0 0 0 0 0 0 0 0 E1h PW23CS 0 0 0 0 0 0 0 0 E2h PW01CON 0 0 0 0 0...

Page 9: ...4 SP 3 SP 2 SP 1 SP 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 1 RW 1 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset SP 7 0 Bits 7 0 Stack Pointer This stack pointer identifies the location wher...

Page 10: ...t DPS 0 is set DPL1 and DPH1 are used in place of DPL and DPH during DPTR operations Data Pointer Select DPS 7 6 5 4 3 2 1 0 SFR 86h ID1 ID0 TSL0 SEL RW 0 RW 0 RW 0 R 0 R 0 R 0 R 0 RW 0 R Unrestricted...

Page 11: ...7 are converted to the Framing Error FE flag for the respective Serial Port OFDF Bit 5 Oscillator Fail Detect Flag This bit is set if a reset is caused by oscillator failure and must be cleared by so...

Page 12: ...overflow has been detected 1 Timer 0 has overflowed its maximum count TR0 Bit 4 Timer 0 Run Control This bit enables disables the operation of Timer 0 Halting this timer will preserve the current coun...

Page 13: ...ode 0 8 bit with 5 bit prescale 0 1 Mode 1 16 bit with no prescale 1 0 Mode 2 8 bit with auto reload 1 1 Mode 3 Timer 1 is halted but holds its count GATE Bit 3 Timer 0 Gate Control This bit enables d...

Page 14: ...Read W Unrestricted Write n Value after Reset TL1 7 0 Bits 7 0 Timer 1 LSB This register contains the least significant byte of Timer 1 Timer 0 MSB TH0 7 6 5 4 3 2 1 0 SFR 8Ch TH0 7 TH0 6 TH0 5 TH0 4...

Page 15: ...21 224 0 00 216 219 222 225 X 01 217 220 223 226 X 10 217 220 223 226 X 11 225 228 231 234 T2M Bit 5 Timer 2 Clock Select This bit controls the division of the system clock that drives Timer 2 This bi...

Page 16: ...MOVX Select 2 0 These bits select the time by which external MOVX cycles are to be stretched This allows slower memory or peripherals to be accessed without using ports or manual software interventio...

Page 17: ...ion on this pin will cause the value in the T2 registers to be transferred into the capture registers if enabled by EXEN2 T2CON 3 When in auto reload mode a 1 to 0 transition on this pin will reload t...

Page 18: ...ng modified is removed and clock multiplier may then be selected as the clock source RGMD Bit 2 Ring Oscillator Mode This bit indicates the status of the ring oscillator If 0 the ring is not being use...

Page 19: ...Multiprocessor communication 11 bits Timer 1 or 2 baud rate equation SM0 FE_0 Bit 7 Framing Error Flag When SMOD0 PCON 6 0 this bit SM0 is used to select the mode for serial port 0 When SMOD0 1 this b...

Page 20: ...n serial port mode 0 TI_0 is set at the end of the 8th data bit In all other modes this bit is set at the end of the last data bit This bit must be manually cleared by software RI_0 Bit 0 Receiver Int...

Page 21: ...g unchanged SWB Bit 5 Switch Back Enable This bit enables 1 or disables 0 the switch back function When enabled switchback will allow the processor to automatically switch from divide by 1024 mode to...

Page 22: ...P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 R Unrestricted Read W Unrestricted Write n Value after Reset P2 7 0 Bits 7 0 Port 2 This port functions as an address bus during...

Page 23: ...Disable all interrupt sources This bit overrides individual interrupt mask settings 1 Enable all individual interrupt masks Individual interrupts will occur if enabled EAD Bit 6 A D Interrupt Enable T...

Page 24: ...Unrestricted Write n Value after Reset CMPL0 7 0 Bits 7 0 Compare Register Zero LSB This register is one of three used to store the least significant 8 bit value for the Timer 2 s comparison function...

Page 25: ...d Read W Unrestricted Write n Value after Reset CPTL0 7 0 Bits 7 0 Capture Register Zero LSB This register is used to capture the least significant 8 bit value for the Timer 2 s channel 0 capture func...

Page 26: ...is set or on the falling edge if the 2 CT CTCON 5 enable is set Setting both enable bits will cause a capture to occur on both edges Capture Register Three LSB CPTL3 7 6 5 4 3 2 1 0 SFR AFh CPTL3 7 CP...

Page 27: ...ral device WR Bit 6 External Data Memory Write Strobe This pin provides an active low write strobe to an external memory or peripheral device T1 Bit 5 Timer Counter External Input A 1 to 0 transition...

Page 28: ...tops ADEX Bit 4 A D External Start When set this bit allows an A D conversion to be initiated by the detection of a falling edge on the STADC pin WCQ Bit 3 Window Comparator Qualifier If set this bit...

Page 29: ...hen the OUTCF bit is cleared the ADMSB will contain the 8 most significant bits and ADLSB will contain the 8 least significant bits of the conversion MUX2 0 Bits 6 4 Multiplexer Select Bits These bits...

Page 30: ...nt Byte This register contains the least significant 8 bits of the A D conversion Note that due to the specific implementation of this register reading back a value written by software will not return...

Page 31: ...s bit controls the priority of the serial port 0 interrupt 0 Serial port 0 priority is determined by the natural priority order 1 Serial port 0 is a high priority interrupt PT1 Bit 3 Timer 1 Interrupt...

Page 32: ...s not compared against the incoming data All incoming data will generate a receiver interrupt if enabled when this register is cleared Slave Address Mask Enable Register 1 SADEN1 7 6 5 4 3 2 1 0 SFR B...

Page 33: ...ns on T2EX will set this bit 0 X 1 Bit toggles whenever timer 2 underflows overflows and can be used as a 17th bit of resolution In this mode EXF2 will not cause an interrupt RCLK Bit 5 Receive Clock...

Page 34: ...CLK or TCLK is set this bit will not function and the timer will function in an auto reload mode following each overflow 0 Auto reloads will occur when timer 2 overflows or a falling edge is detected...

Page 35: ...he Timer 2 compare function This pin will toggle when a match occurs between Timer 2 and compare registers CMPH2 CMPL2 if the enable bit CMTE0 RSTR 6 is set CMSR5 Bit 5 Compare Match Set Reset Pin 5 T...

Page 36: ...t if CMR0 RSTR 0 is 1 and a match occurs between Timer 2 and 16 bit compare register CMPH1 CMPL1 ROM Size Select ROMSIZE 7 6 5 4 3 2 1 0 SFR C2h RS2 RS1 RS0 RT 1 RT 0 RT 0 R Unrestricted Read W Unrest...

Page 37: ...C5 PIP HIP LIP SPTA1 SPRA1 SPTA0 SPRA0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R Unrestricted Read W Unrestricted Write n Value after Reset See description PIP Bit 7 Power Fail Priority Interrupt Status When set...

Page 38: ...e this bit is set or serial port data may be lost SPRA0 Bit 0 Serial Port 0 Receive Activity Monitor When set this bit indicates that data is currently being received by serial port 0 It is cleared wh...

Page 39: ...upt if enabled and software must always clear this bit IE5 CF3 Bit 3 External Interrupt 5 or Capture Interrupt 3 Flag This bit serves as an interrupt flag for External Interrupt 5 and alternatively fo...

Page 40: ...cur only if the enable bit EX2 EC0 EIE 0 is set Setting this bit with software will cause an interrupt if enabled and software must always clear this bit Compare Register 0 MSB CMPH0 7 6 5 4 3 2 1 0 S...

Page 41: ...CPTH0 5 CPTH0 4 CPTH0 3 CPTH0 2 CPTH0 1 CPTH0 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset CPTH0 7 0 Bits 7 0 Capture Register 2 MSB This regi...

Page 42: ...re trigger is enabled by the appropriate bit in register CTCON EBh The least significant 8 bit value is loaded into register CPTL2 AEh Capture Register 3 MSB CPTH3 7 6 5 4 3 2 1 0 SFR CFh CPTH3 7 CPTH...

Page 43: ...order nibble Otherwise it is cleared to 0 by all arithmetic operations F0 Bit 5 User Flag 0 This is a bit addressable general purpose flag for software control RS1 RS0 Bits 4 3 Register Bank Select 1...

Page 44: ...RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset PW1FG 7 0 BitS 7 6 PWM1 Clock Generator Register This register contains the user defined value N wh...

Page 45: ...it PWM operations 16 Bit PWM Mode Enable and A D Reference Select PWMADR 7 6 5 4 3 2 1 0 SFR D6h ADRS PWE1 PWE0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset ADRS Bit 7 A...

Page 46: ...Multiprocessor communication 11 bits Timer 1 baud rate equation SM0 FE_1 Bit 7 Framing Error Flag When SMOD0 PCON 6 0 this bit SM0 is used to select the mode for serial port 1 When SMOD0 PCON 6 1 this...

Page 47: ...de 0 TI_1 is set at the end of the 8th data bit In all other modes this bit is set at the end of the last data bit This bit must be manually cleared by software RI_1 Bit 0 Transmitter Interrupt Flag T...

Page 48: ...Cycle PWM0 256 In 16 bit mode this register is the LSB value register for 16 bit PWM channel 0 and functions identically to 8 bit mode PWM1 Value Register PWM1 7 6 5 4 3 2 1 0 SFR DDh PWM1 7 PWM1 6 PW...

Page 49: ...WM3 7 PWM3 6 PWM3 5 PWM3 4 PWM3 3 PWM3 2 PWM3 1 PWM3 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 R Unrestricted Read W Unrestricted Write n Value after Reset PWM3 7 0 Bits 7 0 PWM3 Value Register This r...

Page 50: ...illator 4 0 1 0 Crystal Oscillator 16 0 1 1 Crystal Oscillator 64 1 x x PWMC0 input pin PW0EN Bits 4 PWM0 Clock Generator Enable This bit enables 1 or disables 0 the clock generator for 8 bit PWM chan...

Page 51: ...se bits operate as indicated in the above description of PW01CS PW3EN Bit 0 PWM3 Clock Generator Enable This bit enables 1 or disables 0 the clock generator for 8 bit PWM channel 3 This bit has no eff...

Page 52: ...e and has no meaning in 16 bit mode PW1DC Bit 2 PWM1 DC Overdrive Setting this bit to a 1 forces the 8 bit PWM channel 1 to output a 1 regardless of the PWM match value This bit has no meaning in 16 b...

Page 53: ...When this bit is cleared reset default condition a read or write to register PWM2 accesses the compare register portion of the PWM2 Pulse Generator When this bit is set a read or write to register PWM...

Page 54: ...to Reload Register LSB This register holds the LSB of the 16 bit reload value when Timer 2 is configured in auto reload mode 2 RL CP 0 Timer 2 Auto Reload Register MSB RLOADH 7 6 5 4 3 2 1 0 SFR E7h R...

Page 55: ...it 3 External Interrupt 5 or Capture 3 Interrupt Enable This bit enables 1 or disables 0 interrupts initiated by the proper transition on the INT5 CT3 pin P1 3 If the capture function associated with...

Page 56: ...2 8 bit overflow sets TF2B flag T2SEL 4 Clearing this bit disables this interrupt Bit 5 Reserved Read data will be indeterminate TF2B Bit 4 Timer 2 8 Bit Overflow Flag This bit is set by hardware when...

Page 57: ...2 on the falling edge of the signal on pin INT4 CT2 P1 2 When set this bit also configures External Interrupt 4 to respond to a negative edge if enabled Clearing this bit disables both capture and int...

Page 58: ...r pair CPTH0 CPTL0 on the rising edge of the signal on pin INT2 CT0 P1 0 When set this bit also configures External Interrupt 2 to respond to a positive edge if enabled Clearing this bit disables both...

Page 59: ...is bit disables this function CMS4 Bit 4 Compare Match Set Enable 4 Setting this bit enables the set function on port pin CMSR4 P4 4 when the contents of Timer 2 and the 16 bit register pair CMPH0 CMP...

Page 60: ...reset function CMR4 Bit 4 Compare Match Reset Enable 4 Setting this bit enables the reset function on port pin CMSR4 P4 4 when the contents of Timer 2 and the 16 bit register pair CMPH1 CMPL1 match C...

Page 61: ...below The associated Port 6 latch bit must contain a logic one before the pin can be used in its alternate function capacity STADC Bit 7 Start A D Conversion If enabled by ADEX ADCON1 4 1 a negative t...

Page 62: ...et PT2 Bit 7 Timer 2 Overflow Interrupt Priority The Timer 2 overflow interrupt request will be high when this bit is 1 and normal priority when it is 0 PCM2 Bit 6 Compare Match 2 Interrupt Priority T...

Page 63: ...e generator 0 Serial Port 1 baud rate will be that defined by baud rate generation equation 1 Serial Port 1 baud rate will be double that defined by baud rate generation equation POR Bit 6 Power on Re...

Page 64: ...y watchdog timer reset It is cleared by a power on reset but otherwise must be cleared by software before the next reset of any kind or software may erroneously determine that a watchdog timer reset h...

Page 65: ...le crystals when high frequency operation is required An illustration of the clock multiplier function specifically and overall system clock generation and control is shown in Figure 5 1 SYSTEM CLOCK...

Page 66: ...by four state For example to change from 00 frequency multiplier to 11 PMM the software must change the bits in the following sequence 00 10 11 Attempts to switch between invalid states will fail lea...

Page 67: ...ys had an INC DPTR instruction users have often wished for the ability to decrement the data pointers as well To maintain instruction set compatibility the DS87C550 supports a decrement data pointer f...

Page 68: ...ad source data byte toggle select bit 2 MOVX DPTR A Store at destination toggle select bit 2 INC DPTR Increment source address toggle select bit 3 INC DPTR Increment destination address toggle select...

Page 69: ...l clock period each In older members of the family there is no further change in setup and hold times regardless of the stretch value selected In the DS87C550 however when a stretch value of 4 or abov...

Page 70: ...d below Power Management Modes Power management mode 2 divide by 1024 is supported on the DS87C550 However power management mode 1 divide by 256 is not Switching between clock sources The ring oscilla...

Page 71: ...flag OFDF PCON 5 bit is set by hardware when the processor enters reset This bit must be cleared by software RST Pin as an Output The DS87C550 is the first member of Dallas High Speed Microcontroller...

Page 72: ...pin of the DS87C550 If the RST pin is too heavily loaded capacitance it may be necessary to add a pull up resistor to speed up the low to high transition This will of course determine what type of out...

Page 73: ...EIP 0 Compare Match 0 2Bh 6 CM0F T2IR 4 ECM0 EIE 4 PCM0 EIP 4 Ext Interrupt 1 3Bh 7 IE1 TCON 3 EX1 IE 2 PX1 IP 2 Ext Interrupt 3 Capture 1 43h 8 IE3 CF1 T2IR 1 EX3 EC1 EIE 1 PX3 PC1 EIP 1 Compare Matc...

Page 74: ...7 P4 3 CMSR3 Timer 2 compare match set reset output 3 P1 0 INT2 CT0 External Interrupt 2 Capture Trigger 0 P4 4 CMSR4 Timer 2 compare match set reset output 4 P1 1 INT3 CT1 External Interrupt 3 Captur...

Page 75: ...t timer counter 13 bit timer counter 16 bit timer counter 16 bit timer counter 16 bit timer counter 16 bit timer with capture 8 bit timer w auto reload 8 bit timer w auto reload 16 bit auto reload tim...

Page 76: ...ERRUPT TL0 TL1 TH0 TH1 TF0 TCON 5 TF1 TCON 7 OSC 4X 2X CD1 0 CLK OUT 1 00 1 0 00 2 x 10 4 x 11 1024 CD1 0 CLK OUT 11 3 072 anything else 12 CLK TIMER 1 FUNCTIONS SHOWN IN PARENTHESIS TIMER COUNTER 0 M...

Page 77: ...rved 1 0 X 12 4 1 1 X 3 072 1 024 Where TxM is either the T0M or T1M SFR bit TIMER 2 As stated earlier the functionality of Timer Counter 2 in the DS87C550 is a superset of the functions found on earl...

Page 78: ...RRUPT TL2 RCAP2L TR2 T2CON 2 TH2 RCAP2H EXF2 T2CON 6 TF2 T2CON 7 T2EX P1 5 b DCEN 1 0FFh 0FFh UP COUNTING RELOAD VALUE DOWN COUNTING RELOAD VALUE COUNT DIRECTION 1 UP 0 DOWN 0 7 8 16 0 7 8 16 0 7 8 15...

Page 79: ...ways i e counter timer auto reload etc and still be used for the capture mode Regardless of the meaning of Timer 2 s value it is this timer s output that is captured under the pre established conditio...

Page 80: ...8 bit concatenated compare registers CMPH0 CMPL0 CMPH1 CMPL1 CMPH2 CMPL2 These compare registers are initialized by the user s software and when if a match occurs between Timer 2 s output and one or m...

Page 81: ...2 CMS2 SETR 2 CMR3 RSTR 3 CMS3 SETR 3 CMR4 RSTR 4 CMS4 SETR 4 CMR5 RSTR 5 CMS5 SETR 5 CMTE0 RSTR 6 CMTE1 RSTR 7 P4 1 Pin P4 2 Pin P4 3 Pin P4 4 Pin P4 5 Pin P4 6 Pin P4 7 Pin WATCHDOG TIMER The DS87C...

Page 82: ...TIME OUT PERIOD in clocks Table 11 3 4X X 2 CD1 0 WD1 0 00 WD1 0 01 WD1 0 10 WD1 0 11 1 00 215 218 221 224 0 00 216 219 222 225 X 01 217 220 223 226 X 10 217 220 223 226 X 11 225 228 231 234 WATCHDOG...

Page 83: ...ized that it would be possible for the oscillator to stop functioning at a time when the processor was commanding some external action to take place Since in this case there is no oscillator to drive...

Page 84: ...the A D LSB result register ADLSB A prescaler clock divider is included which allows a wide range of conversion clock frequencies to be selected A D CONVERTER BLOCK DIAGRAM Figure AD1 ADC0 ADC1 ADC2...

Page 85: ...ntinuous polling and clearing the EOC bit would be required At the end of a conversion the result is latched into a 10 bit latch and is made available to the two A D result registers ADMSB and ADLSB A...

Page 86: ...Enable A D Interrupt IE 6 bit must be set Additionally as with all interrupts the global interrupt enable bit EA IE 7 must be set before any interrupt will be acknowledged The A D interrupt is also q...

Page 87: ...st thing to recognize is that the comparison takes place between the 8 MSbs of the A D result and the 8 bit WINHI and WINLO registers which leaves the two LSBs of the result unused Converting the base...

Page 88: ...16 BIT PWMO1 PIN 8 BIT only PWMO2 PIN 8 or 16 BIT PWMO3 PIN 8 BIT only SYSTEM CLOCK PWMC0 PIN PWMC1 PIN PWM 0 CLOCK GENERATOR PWM 1 CLOCK GENERATOR PWM 2 CLOCK GENERATOR PWM 3 CLOCK GENERATOR For 16 B...

Page 89: ...fined as PWM Clock prescaler Output N 1 where N contents of PWxFG register or N prescaler Output PWM Clock 1 Therefore if the frequency generator register PW0FG PW1FG PW2FG or PW3FG is loaded with the...

Page 90: ...WM function generates the PWM output The logical operation of the Pulse Generator section of PWM0 in 8 bit mode is illustrated in Figure PWM3 All other PWM channels operate in a similar fashion From t...

Page 91: ...r to zero The rollover condition of the Pulse Generator from 0FFh to 00h is detected and causes the PWM output to be set as described previously This condition also causes the corresponding flag bit P...

Page 92: ...WM2 loads the LSB and PWM3 loads the MSB Note that in Figure PWM4 all registers and bits associated with the 16 bit PWM0 function are shown without parentheses All registers and bits associated with t...

Page 93: ...k input for 16 bit PWM0 Similarly bits PW2S2 0 and PW2EN PW23CS7 4 will enable the prescaler and will determine the selected PWM Clock input for 16 bit PWM1 Bits PW01CS3 0 and PW23CS3 0 have no effect...

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