DS87C550 High-Speed Microcontroller User’s Guide Supplement
26 of 93
Capture Register Two LSB (CPTL2)
7
6
5
4
3
2
1
0
SFR AEh
CPTL2.7
CPTL2.6
CPTL2.5
CPTL2.4
CPTL2.3
CPTL2.2
CPTL2.1
CPTL2.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
CPTL2.7-0
Bits 7-0
Capture Register Two LSB.
This register is used to capture the least significant
8-bit value for the Timer 2’s channel 2 capture function. When a transition
occurs on the INT4/CT2 pin, the LSB of Timer 2 is captured in this register on
the rising edge if the CT2=CTCON.4 enable bit is set or on the falling edge if the
2
CT
=CTCON.5 enable is set. Setting both enable bits will cause a capture to
occur on both edges.
Capture Register Three LSB (CPTL3)
7
6
5
4
3
2
1
0
SFR AFh
CPTL3.7
CPTL3.6
CPTL3.5
CPTL3.4
CPTL3.3
CPTL3.2
CPTL3.1
CPTL3.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
CPTL3.7-0
Bits 7-0
Capture Register Three LSB.
This register is used to capture the least
significant 8-bit value for the Timer 2’s channel 3 capture function. When a
transition occurs on the INT5/CT3 pin, the LSB of Timer 2 is captured in this
register on the rising edge if the CT3=CTCON.6 enable bit is set or on the falling
edge if the
3
CT
=CTCON.7 enable is set. Setting both enable bits will cause a
capture to occur on both edges.
