DS87C550 High-Speed Microcontroller User’s Guide Supplement
42 of 93
Capture Register 2 MSB (CPTH2)
7
6
5
4
3
2
1
0
SFR CEh CPTH2.7
CPTH2.6
CPTH2.5
CPTH2.4
CPTH2.3
CPTH2.2
CPTH2.1
CPTH2.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
CPTH2.7-0
Bits 7-0
Capture Register 2 MSB.
This register loads the most significant 8-bit value of
Timer 2 when a transition occurs on the INT4/CT2 pin if the corresponding
capture trigger is enabled by the appropriate bit in register CTCON (EBh). The
least significant 8-bit value is loaded into register CPTL2 (AEh).
Capture Register 3 MSB (CPTH3)
7
6
5
4
3
2
1
0
SFR CFh CPTH3.7
CPTH3.6
CPTH3.5
CPTH3.4
CPTH3.3
CPTH3.2
CPTH3.1
CPTH3.0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
RW-0
R=Unrestricted Read, W=Unrestricted Write, -n=Value after Reset
CPTH3.7-0
Bits 7-0
Capture Register 3 MSB.
This register loads the most significant 8-bit value of
Timer 2 when a transition occurs on the INT5/CT3 pin if the corresponding
capture trigger is enabled by the appropriate bit in register CTCON (EBh). The
least significant 8-bit value is loaded into register CPTL3 (AEh).
