DS87C550 High-Speed Microcontroller User’s Guide Supplement
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using Timer 2. Registers SETR and RSTR contain bits to enable this function. If a match occurs between
Timer 2’s output and CMPH0:CMPL0, port pins P4.0 to 4.5 are set when the corresponding bits in the set
enable register (SETR) are logic 1. If the match is with CMPH1:CMPL1, port pins 4.0 to 4.5 are reset
when the corresponding bits of the reset/toggle enable register (RSTR) are logic 1. A match with
CMPH2:CMPL2 toggles port pins P4.6 and P4.7 if the corresponding bits in the reset/toggle enable
register (RSTR) are logic 1. If any of the bits in SETR or RSTR are 0, then the corresponding port pin
function is disabled. This functionality is further illustrated in Figure 11-8.
TIMER/COUNTER 2 COMPARE MODE:
Figure 11-8.
Reset
Set
Reset
Reset
Reset
Reset
Reset
Set
Set
Set
Set
Set
P4.0
Pin
SETR.6
Toggle
SETR.7
Toggle
C
O
M
P
A
R
E
(C
M
P
H
2
:
C
M
P
L
2
)
C
O
M
P
A
R
E
(C
M
P
H
1
:
C
M
P
L
1
)
C
O
M
P
A
R
E
(C
M
P
H
0
:
C
M
P
L
0
)
T
IM
E
R
2
(T
H
2
:
T
L
2
)
CMR0
(RSTR.0)
CMS0
(SETR.0)
CMR1
(RSTR.1)
CMS1
(SETR.1)
CMR2
(RSTR.2)
CMS2
(SETR.2)
CMR3
(RSTR.3)
CMS3
(SETR.3)
CMR4
(RSTR.4)
CMS4
(SETR.4)
CMR5
(RSTR.5)
CMS5
(SETR.5)
CMTE0
(RSTR.6)
CMTE1
(RSTR.7)
P4.1
Pin
P4.2
Pin
P4.3
Pin
P4.4
Pin
P4.5
Pin
P4.6
Pin
P4.7
Pin
WATCHDOG TIMER
The DS87C550 contains a watchdog timer that is very similar to that found in other members of the high-
speed microcontroller family. It is driven directly off of the internal crystal oscillator (or external clock
attached to XTAL1), and offers several divider chains to provide a wide variety of time-out selections.
The watchdog timer in the DS87C550 is slightly different in several minor ways from that found in other
high-speed microcontrollers. For one, the available divisors and hence the resulting time-out values are
different. In earlier members of the family, divisors of 2
17
, 2
20
, 2
23
, and 2
26
were available. In the
DS87C550, divisors of 2
15
, 2
18
, 2
21
, and 2
24
are available. Additionally, the system clock generation offers
divisors of 1, 2, 3 and 256. Combining these two divisor chains, watchdog time-out periods ranging from
993 us to 130.2 s (2
15
to 2
32
) are possible with a 33 MHz crystal (or oscillator). With a crystal of 11.0952
MHz, time-out values from 2.963 ms up to 387.1 s (6.42 minutes) are possible. As can be seen, the
