Cypress PSoC CY8CTMG20 Series, Technical Reference Manual

Page: 303 / 308

303
Index
Numerics
16-Pin Part Pinout 19
24-Pin Part Pinout 20
32 kHz clock selection 67
32-Pin Part Pinout 21
48-Pin Part Pinout 22
A
ACK bit 240
acronyms 18
Address bits
in I2C_SCR register 240
address spaces, CPU core 27
AMUX_CFG register 204
Analog bit
in INT_CLR0 register 243
in INT_MSK0 register 250
analog input, GPIO 56
architecture
PSoC core 23
system resources 105
top level 14
TrueTouch system 83
B
bank 0 registers 188
register mapping table 184
bank 1 registers 259
register mapping table 185
basic paging in RAM paging 39
Bias Trim bits in ILO_TR register 282
Bus Error bit 240
Bypass bit 261
Byte Complete bit 240
C
Calibrate0 function in SROM 37
Calibrate1 function in SROM 37
Carry bit 254
CDSx bits 208
CHAIN bit 212
Checksum function in SROM 37
CIN_EN bit 213
CINTx bits 208
CIP_EN bit 213
CLKSEL bits 212
Clock Phase bit in SPI_CR 192
Clock Polarity bit 192
Clock Rate bits 239
Clock Sel bit 261
clock, external digital 110
switch operation 110
clocks digital, See digital clocks
CMP_CR0 register 104, 207
CMP_CR1 register 104, 208
CMP_LUT register 104, 210
CMP_MUX register 103, 206
CMP_RDC register 103, 205
CMP0D bit 205
CMP0L bit 205
CMP1D bit 205
CMP1L bit 205
CMPxEN bits 207
COHM bit 217
COHS bit 217
COLM bit 217
COLS bit 217
comparators 101
architecture 101
register definitions 103
configuration register in SPI
SPI_CFG register 150
control register in SPI
SPI_CR register 149
conventions, documentation
acronyms 18
numeric naming 17
register conventions 183
core, See PSoC core
CPINx bits 208
CPU core 27
instruction formats 30
instruction set summary 28–29
overview 27
register definitions 32
CPU Speed bits 276
CPU_F register 32, 254
CPU_SCR0 register 138, 258
CPU_SCR1 register 65, 257
CRSTx bits 208
CS_CNTH register 94, 216
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